1. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 1 Raimund Ubar Tallinn Technical University D&T Laboratory Estonia Test Generation and Fault Simulation for Digital Systems Kharkov National University of Radioelectronics Kharkov, Ukraine April 5-7, 2004

2. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 2 Motivation of the Course The increasing complexity of VLSI circuits has made test generation one of the most complicated and time-consuming problems in digital design The more complex are getting systems, the more important will be the problems of test and design for testability because of the very high cost of testing electronic products Engineers involved in SoC design and technology should be –made better aware of the importance of test, –very close relationships between design and test, and –trained in test technology to enable them to design and produce high quality, defect-free and fault-tolerant products

3. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 3 Goals of the Course The main goal of the course is to give the basic knowledge to answer the question: How to improve the testing quality at increasing complexities of today's systems? This knowledges includes –understanding of how the physical defects can influence on the behavior of systems, and how the fault modelling can be carried out –learning the basic techniques of fault simulation, test generation and fault diagnosis –understanding the meaning of testability, and how the testability of a system can be measured and improved –learning the basic methods of making systems self-testable The goal is also to give some hands-on experience of solving test related problems

4. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 4 Objective of the Course Specification Hardware description languages (VHDL) Implementation Full custom, standard cell, gate arrays Manufacturing CMOS VLSI Design Flow Testing Fault modeling Test generation Fault simulation Verification Simulation. Timing analysis, formal verification

5. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 5 Test Environment Test System Fault dictionary System model Test generation Fault simulation Test result Fault diagnosis Go/No go Located defect Test experiment Test tools (BIST)

6. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 6 Topics Map Models Theory Tools Fault Modelling Defect Level High Level System Modelling High Level Logic Level Boolean Differential Analysis BDD Decision Diagrams Hierarchical approaches Fault Simulation Test Generation

7. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 7 Abstract How to improve the testing quality at increasing complexities of today's systems? Two main trends: defect-oriented test and high-level modelling –Both are caused by the increasing complexities of systems based on deep- submicron technologies The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used Trends to high-level modelling and defect-orientation are opposite As a promising compromise and solution is: to combine hierarchical approach with defect orientation Decision Diagrams serve as a good tool for hierarchical modelling of defects in digital systems

8. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 8 Outline Introduction to Digital Test (5) How to improve test quality at increasing complexity of systems (9) High-level modelling and defect-orientation (25) BDDs and logic level testing Hierarchical test generation (42) –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation (62) Overview of tools developed at D&T Lab (70)

9. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 9 Introduction: the Problem is Money? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams Test coverage function Time 100%

10. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 10 Introduction Paradox 1: Digital world is finite, analog world is infinite. However, the complexity problem was introduced by Digital World Paradox 2: If I can show that the system works, then it should be not faulty. But, what does it mean: it works? 32-bit accumulator has 2 64 functions which all should work. So, you should test all the 2 64 functions ! All life is an experiment. The more experiments you make, the better (American Wisdom) System Stimuli Y Response X Y X Analog case (samples) Digital case (“continuous”)

11. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 11 Introduction: How Much to Test? Paradox: 2 64 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 2 65 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Time can be your best friend or your worst enemy (Ray Charles) & & x1x1 x2x2 x3x3 y State q Y = F(x 1, x 2, x 3,q) * 1 1 Y = F(x 1, x 2, x 3 ) Bridging fault 0

12. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 12 Introduction: Hierarchy Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates

13. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 13 Introduction: Design for Testability Amusing testability: Theorem: You can test an arbitrary digital system by only 3 test patterns if you design it approprietly & 011 101 001 & 011 101 001 & ? & 011 101 001 1 010 & 011 101 001 Solution: System  FSM  Scan-Path  CC  NAND Proof:

14. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 14 Introduction: Quality Policy Quality policy Yield (Y) P,n Defect level (DL) P a Design for testability Testing P - probability of a defect n - number of defects P a - probability of accepting a bad product - probability of producing a good product

15. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 15 Introduction: Defect Level DL T(%) YY 1000 1 Y(%) T(%) 10 50 90 5090 851 45255 81459 DL   T  Paradox: Testability   DL 

16. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 16 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

17. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 17 Complexity vs. Quality Problems: Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies New solutions: The complexity can be reduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels –But this moves us even more away from the real life of defects (!) To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used –But, this is increasing even more the complexity (!) To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

18. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 18 Fault and defect modeling Defects, errors and faults An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults - defects Physical faults do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with fault models System Component Defect Error Fault

19. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 19 Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

20. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 20 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Generic function with defect: Function: Faulty function: A transistor fault causes a change in a logic function not representable by SAF model Defect variable: d =d = 0 – defect d is missing 1 – defect d is present Mapping the physical defect onto the logic level by solving the equation:

21. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 21 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

22. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 22 Why Boolean Derivatives? Distinguishing function: Given: BD-based approach: Using the properties of BDs, the procedure of solving the equation becomes easier

23. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 23 Functional Fault vs. Stuck-at Fault No Full SAF-TestTest for the defect x1x1 x2x2 x3x3 x4x4 x5x5 x1x1 x2x2 x3x3 x4x4 x5x5 1 1110-10-01 2 0--111-001 3 0110101110 4 10110 5 1100- Full 100% Stuck-at-Fault-Test is not able to detect the short: The full SAF test is not covering any of the patterns able to detect the given transistor defect  Functional fault

24. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 24 Defect coverage for 100% Stuck-at Test Results: the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

25. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 25 Generalization: Functional Fault Model Constraints calculation: y Component F(x 1,x 2,…,x n ) Defect WdWd Component with defect: Logical constraints Fault-free Faulty Fault model: (dy,W d ), (dy,{W k d }) Constraints: d = 1, if the defect is present

26. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 26 Functional Fault Model Examples y Component F(x 1,x 2,…,x n ) Defect WdWd Constraints examples: Component with defect: Logical constraints Constraints: FF model: (dy,W d ), (dy,{W k d })

27. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 27 Functional Fault Model for Stuck-ON Stuck-on x1x1 x2x2 Y V DD V SS x1x1 x2x2 NOR gate Conducting path for “10” RNRN RPRP x1x1 x2x2 yydyd 0011 0100 100Z: V Y 1100 Condition of the fault potential detecting:

28. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 28 Functional Fault Model for Stuck-Open Stuck-off (open) x1x1 x2x2 Y V DD V SS x2x2 NOR gate No conducting path from V DD to V SS for “10” x1x1 Test sequence is needed: 00,10 x1x1 x2x2 yydyd 0011 0100 100Y’ 1100 t x 1 x 2 y 1 0 0 1 2 1 0 1

29. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 29 Functional Fault Model Example: Bridging fault between leads x k and x l The condition means that in order to detect the short between leads x k and x l on the lead x k we have to assign to x k the value 1 and to x l the value 0. xkxk xlxl x* k d Wired-AND model x k *= f(x k,x l,d)

30. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 30 Functional Fault Model Example: x1x1 x2x2 x3x3 y & & x1x1 x2x2 x3x3 y & & & Equivalent faulty circuit: Bridging fault causes a feedback loop: Sequential constraints: A short between leads x k and x l changes the combinational circuit into sequential one t x 1 x 2 x 3 y 1 0 2 1 1 1 1

31. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 31 First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System Component Low level k WFkWFk WSkWSk Environment Bridging fault Mapping High level

32. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 32 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect- orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

33. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 33 Register Level Fault Models K: ( If T,C) R D  F(R S1, R S2, … R Sm ),  N RTL statement: K- label T- timing condition C- logical condition R D - destination register R S - source register F- operation (microoperation)  - data transfer  N- jump to the next statement Components (variables) of the statement: RT level faults: K  K’- label faults T  T’- timing faults C  C’- logical condition faults R D  R D - register decoding faults R S  R S - data storage faults F  F’- operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults

34. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 34 Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer ( n inputs log 2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

35. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 35 Fault models and Tests Dedicated functional fault model for multiplexer: –stuck-at-0 (1) on inputs, –another input (instead of, additional) –value, followed by its complement –value, followed by its complement on a line whose address differs in one bit Functional fault model Test description

36. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 36 Faults and Test Generation Hierarchy Circuit Module System Network of gates Gat e Functional approach F ki Test F k W F ki W S F Test W F k W S k Structural approach Network of modules W d ki Interpretation of W F k : - as a test on the lower level - as a functional fault on the higher level Higher Level Module Component Lower level kiki W F ki W S ki Environment Bridging fault k WFkWFk

37. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 37 Hierarchical Defect-Oriented Test Analysis BDDs DDs

38. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 38 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

39. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 39 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: 0 1 1 0 1 0 0 Boolean derivative: 1 0 Functional BDD

40. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 40 Elementary Binary Decision Diagrams Elementary BDDs: 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 & x2x2 x3x3 y x1x1 x1x1 x2x2 x3x3 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 + x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 yx2x2 x3x3 Adder NOR AND OR

41. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 41 Building a SSBDD for a Circuit & 1 1 x1x1 x2x2 x3x3 x 21 x 22 y a b a b y a x1x1 x 21 b x 22 x3x3 a y x3x3 y x3x3 x1x1 x 21 DD-library: Superposition of DDs  Superposition of Boolean functions: Given circuit: Compare to SSBDD Structurally Synthesized BDDs: ba

42. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 42 Representing by SSBDD a Circuit & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 y = c y e y = c y  e y = x 6,e,y x 73,e,y  d ey b ey y = x 6 x 73  ( x 1  x 2 x 71 ) ( x 5  x 72 ) Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds

43. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 43 Fault modeling on SSBDDs The nodes represent signal paths through gates Two possible faults of a DD-node represent all the stuck-at faults along the signal path & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 Test pattern: 1 2 3 4 5 6 7 y 1 1 0 0 1 1

44. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 44 Boolean Operations with BDDs AND-operation: 1 & & x1x1 x2x2 x3x3 x 21 x 22 y a b 1 & & x5x5 x6x6 x51x51 x52x52 c d x4x4 g e y = e  g x3x3 x1x1 x 21 x 22 x6x6 x4x4 x51x51 x52x52 y OR-operation: x3x3 x1x1 x 21 x 22 y x6x6 x4x4 x51x51 x52x52 y = e  g

45. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 45 Boolean Operations with BDDs Boolean function:Inverted function: Dual function:Inverted dual function: y = x 1 x 2  x 3 y = x 1 x 2  x 3 = (x 1  x 2 ) x 3 x1x1 x2x2 x3x3 y x1x1 x3x3 x2x2 y x1x1 x3x3 x2x2 y* y*= (x 1  x 2 ) x 3 y * = x 1 x 2  x 3 x1x1 x2x2 x3x3 y *

46. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 46 BDD and DNF/KNF Boolean function: y = x 1 x 2  x 3 (x 4  x 5 x 6 ) x1x1 x2x2 x3x3 x5x5 x6x6 x4x4 1 y x 3 x 5 x 6 = 1 x1x1 x2x2 x3x3 x5x5 x6x6 x4x4 y x 1 x 4 x 5 = 1 0 Each 1-path represents a term in the DNF, each 0-path represents a term in the KNF

47. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 47 Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 1 0 - 1 Testing Stuck-at-0 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 12  0, x 21  0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0

48. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 48 Example: Test Generation with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 1 1 1 Test pattern: 1 0 Tested faults: x 12  0, x 31  0, x 4  0 Testing Stuck-at-0 faults on paths:

49. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 49 Example: Test Generation with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 0 1 1 0 1 Test pattern: 1 0 Tested faults: x 13  1, x 22  0, x 32  0 Testing Stuck-at-0 faults on paths:

50. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 50 Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 0 0 1 1 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 11  1, x 12  1, x 22  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1

51. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 51 Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 0 1 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 21  1, x 31  1, x 13  0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1

52. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 52 Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 1 0 1 0 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested fault: x 4  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1 Not yet tested fault: x 32  1

53. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 53 Transformation of BDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x4x4 x3x3 x2x2 SSBDD: Optimized BDD: x1x1 y x2x2 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x12x12 x3x3 x4x4 x13x13 x22x22 x32x32 x1x1 y x2x2 x4x4 x3x3 x2x2 x3x3 BDD:

54. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 54 Example: Test Generation with BDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y D 1 0 - D Testing Stuck-at faults on inputs: Test pair D=0,1: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 1  0, x 1  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 x1x1 y x2x2 x4x4 x3x3 x2x2 SSBDD: BDD:

55. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 55 Deductive Fault Simulation & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y Fault list calculation: L a = L 4  L 5 L b = L 1  L 2 L c = L 3  L a L y = L b - L c ----------------------------------------------------------- L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Gate-level fault list propagation L a – faults causing erroneous signal on the node a L y – faults causing erroneous signal on the node a

56. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 56 Deductive Fault Simulation with DDs Macro-level fault propagation: & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y Fault list propagated: L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) 12 34 5 y Fault list calculation on the DD L y = ( L 1  L 2 ) L y = ( L 1  L 2 ) - L 3 L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Faults on the activated path: First order fault masking effect: Second order fault masking effect:

57. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 57 Critical Path Tracing & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y 12 34 5 y Problems : & & 1 1 1 0/1 y & & 1 1 0 1 y 1/0 1 1 1 1 The critical path is not continuous The critical path breaks on the fan-out

58. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 58 Fault Diagnosis with SSBDDs Guided-probe testing at the macro-level & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 1 0 0 1 0 1 1 1 1 6 7373 1 2 5 7272 7171 y 0 1 There is a fault on the line 7 1 Nodes to be pinpointed: Gate level: c, e, d, 1, a, 7 1 (6 attempts) Macro level (DD): 1, 7 1 (2 attempts) Rules on DDs: Only the nodes where the leaving direction coincides with the leaving direction from the DD should be pinponted If simulation shows that these nodes cannot explain the faulty behavior they can be dropped 0 1

59. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 59 SSBDDs vs. BDDs Advantages of SSBDDs compared to the BDDs: Complexity explosion is avoided –The number of nodes is linear with the circuit size (determined by the number of paths in macros) Test-specific structural features can be represented –Each node represent a signal path in the circuit –Faults of the circuit are directly represented in SSBDDs –Circuit’s dynamic (hazards, risk, delays) can be investigated with SSBDDs Processing speed can be increased due to special properties of SSBDDs –Test generation (search space can be reduced) –Fault simulation (the speed of fault analysis can be increased) –Fault diagnosis (minimization of experiments easily controlled) Disadvantage: SSBDDs cannot be minimized

60. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 60 SSBDDs vs. BDDs Increasing the Speed of Test Generation with SSBDDs NA B Theorem: In SSBDD there exists always a path between the two successors A and B of N, either from A to B or from B to A 1 23 4 5 9 6 78 11 10 0 1 Breake search here Task: Activate a path to 1 Important property of SSBDD: Result: Tracing is forced in nodes 1,9,10  Output 0 Another trials possible from 2,3,4  Not needed

61. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 61 SSBDDs vs. BDDs Increasing the Speed of Fault Simulation with SSBDDs Theorem: If a path in SSBDD is activated by a test pattern to 0 (or 1), then no faults can be detected by this pattern at nodes left in the oposite direction 1 (or 0) & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro Example: 6 7373 1 2 5 7272 7171 y 1 The activated path is shown in bold The output value is 1 No need of fault simulation in nodes 6 and 1

62. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 62 SSBDDs vs. BDDs Increasing the Speed of Fault Location with SSBDDs Theorem: If a path in SSBDD is activated to 0 (or 1), and an error is observed on the output, then no faults at nodes left in oposite direction 1 (or 0) can be the causes of the error Error detected Error signal traced C Circuit under guided probing:... Where to continue pinpointing? SSBDD for the component C: 1 23 4 5 6 8 1 7 The activated path is shown in bold The output value is 0 Faults can be detected only in nodes 1,6,7

63. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 63 SSBDDs vs. Gate-Level Models Advantages of SSBDDs compared to the Gate-Level Models: Complexity reduction –Faults domain: each node represent all the faults of the corresponding signal path (fault collapsing) –Time domain: each node represent the delay of the corresponding signal path Hierarchical approaches are easy –SSBDD for a subcircuit can be represented as a macro –No special manipulation procedures for different macros are needed –No model libraries for different tools are needed

64. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 64 Extensions of BDDs –1980 - Multi-Terminal DDs for uncertainty in sequential circuits (1993) Automatika I Telemehanika, No5, 1980 –1981 - Word-Level DDs for Data-Paths Nachrichtentechnik-Elektronik 31 (1981, H.1) –1983 - DDs with multi-output internal nodes Proceedings of TTU No. 550 –1983 - Vector DDs for output behaviour of microprocessors Fault-Tolerant Computing Symposium, Milano Recent papers on high-level DDs: –R.Ubar. Test Synthesis with Alternative Graphs. J.of IEEE Design and Test of Computers. Spring, 1996, pp.48-59 –R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. J. of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38, pp.317-329, 1998 –J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. of Electronic Testing. Kluwer Acad. Publ. Vol. 16, No. 3, pp. 213-226, 2000. –R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with DDs. IEEE ISCAS’2000 Conf., Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

65. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 65 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

66. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 66 Hierarchical Test Generation In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes These modes will usually contain: –a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or –a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) In the hierarchical approach, top-down and bottom-up strategies can be distinguished

67. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 67 Hierarchical Test Generation Approaches A B C D a D c A = ax D: B = bx C = cx A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a,c,D fixed x - free a’ c’ a Bottom-up approach:Top-down approach: a’,c’,D’ fixed x - free System Module c

68. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 68 Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c A = ax D: B = bx C = cx a,c,D fixed x - free a System Module c

69. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 69 Hierarchical Test Generation Approaches Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a’ c’ a’,c’,D’ fixed x - free System Module

70. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 70 Hierarchical Test Generation on DDs Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram Hierarhical test generation with DDs: Scanning test (defect-oriented) Control: y 1 y 2 y 3 y 4 = x032 Data: For all specified pairs of (R 1, R 2 ) Test program: Low level test data (constraints W)

71. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 71 Test Generation on High Level DDs y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test (High-level faults) Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program: Activating high-level faults:

72. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 72 Gate-level Test Generation Structural gate-level testing: Path activation & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault sensitisation: x 7,1 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: x 7 = D = 0: x 3 = 1, x 4 = 1 b = 1: (already justified) c = 1: (already justified) Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present 1 1 1 1 Test pattern

73. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 73 Defect-Oriented Test Generation Test generation for a bridging fault: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: b = 1: x 5 = 0 y Component F(x 1,x 2,…,x n ) Defect WdWd Activate a path Bridge between leads 7 3 and 6 WdWd 0 1

74. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 74 Test Generation with SSBDDs & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 Test pattern for the node 7 1 at the constraint W d = x 6 x 7 = 1: 1 2 3 4 5 6 7 y 1 1 0 0 1 1 Defect: dx 7 =1: x 7 =0 No fault: dx 7 =0: x 7 =1 Defect W d manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Functional Fault dx 7 propagation: x 1 = 1, x 2 = 1, x 5 = 0 Bridge between leads 7 and 6: (dx 7,W d ) (dx 7,W d )

75. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 75 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C y 2 A 2R’ 2 y 1 R’ 1 3 B F(B,R’ 3 ) A A A  R’ 1  0  0  0 2 Y,R 3 R 2 0 1 1 0 0 2 3 R 1 C R’ 1 1  1 0 0 1 0 2 0 1 0 1 1 C+R’ 2 R’ 3 2 1 Transparency functions on Decision Diagrams: Y = C  y 3 = 2, R 3 ’ = 0 C - to be tested R 1 = B  y 1 = 2, R 3 ’ = 0 R 1 - to be justified + R 3 R 2  F R 1 A B C Y y 2 A y 3 y 1 s High-level path activation on DDs 0 2

76. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 76 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C y 2 2 A 2R’ 2 y 1 R’ 1 3 B F(B,R’ 3 ) A A A  R’ 1  0  0  0 2 Y,R 3 R 2 0 1 1 0 0 2 2 0 3 R 1 C R’ 1 1  1 0 0 1 0 2 0 1 0 1 1 C+R’ 2 R’ 3 2 1 + R 3 R 2  F R 1 A B C Y y 2 A y 3 y 1 s System model Data path Control path q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4

77. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 77 Test Generation for RTL Digital Systems Test generation steps: Fault manifestation Fault-effect propagation Constraints justification y 3 =2 R’ 2 =0 y 2  0 R 3 = D= D A  R’ 1 A = D= D 1 1 = D= D 2 B = D= D 2 3 =0 y 1 =2=2 y 3  0 C = D= D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation for data-path (example): D D1D1 D2D2

78. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 78 Test Generation for RTL Digital Systems Test generation step: Fault-effect propagation y 3 = 2= 2 R’ 2 = 0= 0 y 2 = 0  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 = 0= 0 y 1 = 2= 2 y 3 = 0  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 y 3  0 CR’ 2 C 2 Y,R 3 1 0 0 2 0 C+R’ 2 R’ 3 q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4 D D

79. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 79 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C 2 Y,R 3 0 1 0 0 2 0 y 1 R’ 1 3 B F(B,R’ 3 )  0 R 1 1 0 2 0 C+R’ 2 R’ 3 y 2 2 A 2R’ 2  0R 2 0 1 2 3 R’ 2 Path activation procedures on DDs: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 q’  1001 q y 1 y 2 y 3  4200 1 2 0 R’ 2 =0 1 0 #2120   3021  4211  0112 3 4 Test generation step: Line justification Time: t-1

80. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 80 Test Generation for RTL Digital Systems Symbolic test sequence: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation example:

81. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 81 Test Generation for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

82. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 82 Test Generation for Microprocessors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

83. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 83 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

84. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 84 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

85. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 85 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

86. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 86 Hierarchical fault simulation High-Level component High-Level component High-Level component Sequence of patterns P: First Pattern R: Faults Set of patterns With faults P;P 1 (R 1 )…P n ( R n ) Set of patterns with faults P;P 1 (R 1 )…P m ( R m ) P: Pattern Set of patterns with faults P;P 1 (R 1 )…P n ( R n ) System

87. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 87 Hierarchical fault simulation

88. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 88 Hierarchical fault simulation Definition of the complex pattern: D = {P, (P 1,R 1 ), …, (P k, R k )} P is the fault-free pattern (value) P i (i = 1,2,..., k) are faulty patterns, caused by a set of faults R i All the faults simulated causing the same faulty pattern P i are put together in one group R i R 1 - R k are the propagated fault groups, causing, correspondingly, the faulty patterns P 1 - P k

89. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 89 Fault Simulation with DD-s Fault propagation through a complex RT-level component q xAxA xcxc B C A D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. Decision diagram New D A to be calculated Sub-system for A A 0 1 0 q xAxA B + C A + 1 13 xCxC A + C 04 xAxA A 0 xCxC 2 1 0 A - 1 A + B

90. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 90 Fault Simulation with DD-s Fault propagation through a complex RT-level component D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (2,5)}, D xC = {1, 0 (3,4)}, D A = {7, 3 (3,4,5,7), 4 (1,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. q’x A 1 (1,2,3,4,5) 0 (1,2,3,4,5) A’+1 8 (  ) 9 (8) 5 (9) B’+C’ 0 (1,2,5) 8(  ) + 1(1) = 9(1) 6(2) + 2(2) = 8(2) 3(5) + 4(  ) = 7(5) x A x C A’ 4 (3,4) 0 (4) 1 (3) 0 (4) 2 3 3.4) 1 1 New complex vector for A: D A = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)} This fault is masked 8(2) 4 (7) A’ 4(3)

91. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 91 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation BDDs and logic level testing Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Overview of tools developed at D&T Lab

92. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 92 DECIDER: Hierarchical ATPG R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Modules or subcircuits are represented as word-level DD structures Logic Synthesis Scripts Design Compiler (Synopsys Inc.) Gate Level Descriptions SSBDD Synthesis SSBDD Models of FUs Hierarchical ATPG RTL Model (VHDL) FU Library (VHDL) FU Library (DDs) RTL DD Synthesis Test patterns RTL DD Model

93. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 93 TURBO-TESTER: Low-Level TPG Tools Test Generation BIST Simulation Methods: Deterministic Random Genetic Methods: BILBO CSTP Store/Generate Design Test Levels: Gate Macro Fault Simulation Methods: Single fault Parallel Deductive Fault Table Fault models: Stuck-at-faults Stuck-opens Delay faults Test Optimization Fault Diagnosis Fault Location

94. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 94 Conclusions Physical defects can be formally mapped to the logical level by Boolean differential calculus Functional fault model is a universal means for mapping test results from lower levels to higher levels, giving a formal basis for hierarchical approaches to test generation and fault simulation Decision diagrams is a suitable tool which can be used successfully both, on the logic level, and also on higher register transfer or behavioral levels

95. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 95 References 1.S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p. 2.M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p. 3.M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p. 4.S. Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996, 141 p. 5.R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59. 6.J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. JETTA: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000. 7.R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001, pp.365-371. 8.T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of Microelectronics Reliability, Vol. 42, 2002, pp.1141-114.

96. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 96 References European Projects: –EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II Special thanks to: –EU project IST-2000-30193 REASON –Cooperation partners: IISAS Bratislava, TU Warsaw –Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn) Contact data: –Tallinn Technical University –Computer Engineering Department –Address: Raja tee 15, 12618 Tallinn, Estonia –Tel.: +372 620 2252, Fax: +372 620 2253 –E-mail: raiub@pld.ttu.ee –www.ttu.ee/ ˇ raiub/