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Digital & Analog electronics for an autonomous, deep-sea Gamma Ray Burst Neutrino prototype detector K. Manolopoulos, A. Belias, E. Kappos, C. Markou DEMOKRITOS.

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Presentation on theme: "Digital & Analog electronics for an autonomous, deep-sea Gamma Ray Burst Neutrino prototype detector K. Manolopoulos, A. Belias, E. Kappos, C. Markou DEMOKRITOS."— Presentation transcript:

1 Digital & Analog electronics for an autonomous, deep-sea Gamma Ray Burst Neutrino prototype detector K. Manolopoulos, A. Belias, E. Kappos, C. Markou DEMOKRITOS NATIONAL CENTER FOR SCIENTIFIC RESEARCH

2 GRBNeT  Gamma Ray Burst Neutrino Telescope – Development, construction and testing of a prototype autonomous detection unit – anchored at the sea bed without any cabled connection to the shore – able to operate for a prolonged time ( ~1year)  A few tens of such arrays separated by 300-400 meters from each other, will be able to cover a volume of ~ 10km 3 in the deep sea – provide a sufficiently large observational volume – capable of detecting high-energy neutrinos originating from GRBs 2

3 GRBNeT prototype layout Grey spheres: Optical Modules Orange spheres: data acquisition electronics, acoustic communication, power units Green spheres: Buoyancy 40m 200m 130m Detection Unit 3

4  4 Optical Modules arranged in a cross shaped frame  Optical Module: 13-inch PMT (R8055) housed inside a pressure resistant glass sphere – Detects Cherenkov light produced by muons in the deep-sea  Each cluster operates autonomously in terms of – Power supply – data acquisition – trigger systems Optical Modules 4

5 GRBNeT basic characteristics  No dependency on cables – Cost effective & easy to deploy – Can be placed around any active underwater telescope  PMTs look towards the horizon where there is maximum sensitivity for UHE neutrinos – Use high signal thresholds (> 5 p.e) to reduce data rate and minimize background  Deep-sea deployment to reduce atmospheric background  Power will be supplied by batteries at ambient pressure! – Low power electronics  Each floor has its own trigger and DAQ – Synchronization between floors through LED beacons. – Data stored locally and recovered through an acoustic modem or at recovery time. 5

6 Deployment Location  Several locations near Pylos available at various depths  Prototype deployment at 3500m  GRBNeT autonomous prototype lines can also be deployed in other KM3NeT sites 6

7 Block Diagram of the Electronics Container 7 Spartan - 6 FPGA Atomic Clock Multiple Threshold Discriminator Optical Modules Input lines … FMC 10MHz Clock PPS Compass Tilt-meter Microcontroller Acoustic Modem PMTs voltage controller Slow Control Unit Electronics Container

8 8 ANALOG ELECTRONICS

9 PMT base  To minimize power consumption we developed a new PMT base – Cockroft-Walton (CW) voltage multiplier to operate up to 2.5kV – HV-controller with ultra low-power microcontrollers  Each Optical Module features a HV control unit to drive the CW, producing the desired voltage for the specific PMT (R8055) 9

10 Gain vs. High Voltage 10 Comparison between PMTs with CW-base and Resistive-base

11 Multiple Threshold Discriminator Each PMT transmits the analog signal to a multiple threshold level discriminator – 4 thresholds for this prototype are chosen to cover a large dynamic range of PMT signals – Analog signal is compared to a very low, low, medium and a high threshold When a threshold level is crossed the discriminator outputs a digitized pulse – Pulse lasts for as long as the analog signal remains above that threshold. The digitized pulses are used as input to the FPGA 11

12 DIGITAL ELECTRONICS 12

13 FPGA Design Requirements  Detect events of interest, based on PMTs digitized outputs  Measure spatial and temporal characteristics of these events (i.e. duration, intensity)  Use an atomic clock as an autonomous, free-running reference clock for synchronicity and time-stamping  Store the result locally to a permanent data storage  Collect and store operational data and data from auxiliary devices 13

14 Hardware Components FMC XM105 Spartan-6 LX16 Evaluation Kit Chip Scale Atomic Clock 14

15 FPGA Design Block Diagram 15

16 Coincidence Logic Unit  Searches for PMT signals that “coincide” within a small time window  State machine monitors if at least 2 out of 4 PMTs produce a pulse within a 200ns window (2-fold coincidence)  If a 2-fold coincidence is detected – Time window expands to 200ns + 100ns – At the end of the expanded 300ns window all PMT data are stored 16

17 Time Over Threshold calculation Use of different clock domains to calculate coarse time and fine time 17

18 Rate Measurement Unit  Detects incoming pulses (monitoring the every threshold level)  Counts the number of incoming pulses within a programmable time window (i.e. 1sec)  At the end of the time window results are stored to a RAM  Permanent storage of the rate measurements is done periodically 18

19 Writing to SD Card  Communication wit SD cards via SPI protocol  Current estimate of trigger rates ~ 10Hz  Data size of each detected event ~200bytes  Worst-case scenario of continuous 10Hz rate => 7.2Mb/hour => ~63Gb/year (regarding the data rates see also K. Pikounis talk) 19

20 Control Unit – Handles synchronization and control signals – Responsible for data and command handling – Periodically initiate data storage to the SD cards Slow Control Unit – Implemented at a separate board that hosts a PIC microcontroller Controls/monitors the PMTs voltages Communicates via I2C with – Tiltmeter – Compass Communicates with the Acoustic Modem Stores periodically the gathered data to an SD Card 20

21 FPGA Design Implementation Results Implementation Results Slice Registers Slice LUTsOccupied Slices MUXCYsRAMB16 FPGA Design 3098 (17%) 2039 (22%) 1168 (51%) 672 (15%) 25 (78%) 21 FPGA Utilization Total Power375 mW Quiescent Power93mW Dynamic Power282 mW Power Consumption (Xilinx power analyzer)

22 CSAC Atomic Clock Chip Scale Atomic Clock (Microsemi SA) – World’s smallest, lowest power atomic clock technology – Low power consumption (< 125mW) – Enables atomic timing accuracy in portable, battery powered applications – Provides 10 MHz clk and PPS 22 Simplified CSAC block diagram

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25 Conclusions Developed the DAQ system of the GRBNeT autonomous detection unit – Flexible design utilize general purpose FPGA – Compartmentalized functionality – Can easily be adapted to future changes Project is on-going – All aspects of the project are being tested in lab. environment – Preparations for the deployment have started – Schedule for deployment with HCMR R/V "AEGAEO" is being prepared …Stay tuned!!! 25

26 Thank you for your attention!! 26

27 BACKUP SLIDES 27

28 PMT Calibration with the CW-base 28


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