1. Rémi CORNAT (IN2P3/LPC) - PRR june’06 Preshower FE Board design R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq M-L. Mercier, P. Perret cornat@clermont.in2p3.fr

2. Rémi CORNAT (IN2P3/LPC) - PRR june’06 2 Overview : FE board x 64 Clock distribution ECS : GLUE (LAL) Each AX receives 8 SPD bits 8 AX1000 (data proc. + L0) 64 ADC + Op. Amp TRIG : APA450 2*64 trigger bits SPD multiplicity and 2x2 cluster DAQ & TTC : SEQ (LAL) VFE clk & rst Power & delatchers I II III IV

3. Rémi CORNAT (IN2P3/LPC) - PRR june’06 3 PCB & I/Os 12 layers, class 6 LAL backplane & crate 1 test support on one FE_PGA Connector for external USB/I2C generator (needs GLUE modifications) 64 analogue inputs RJ45 connectors Ethernet CAT6 cable 2 clk & 2 rst to VFE Differential ECL on cables 64 SPD inputs Serial LVDS on cables 20 bits to DAQ Serial LVDS on backplane TRIG TOP/BOT neighbours 2*16b serial LVDS on cables TRIG RIGHT/LEFT neigh. 2*18 LVDS on backplane 2 ECAL @+BXID 2*21 bits serial LVDS on cables SPD multiplicity 21b serial LVDS on backplane 2x2 cluster to VALIDATION 2*13b serial LVDS on cables

4. Rémi CORNAT (IN2P3/LPC) - PRR june’06 4 On board data flow Point to point parallel links only – Easy to test with injection and acquisitions RAM in FE, TRIG and SEQ pgas Production Commissioning – JTAG scan path available

5. Rémi CORNAT (IN2P3/LPC) - PRR june’06 5 Tests connectors JTAG – Program (APA) – Test (externally cabled JTAG chain) Tests (SiliconExplorer) – Debugging steps

6. Rémi CORNAT (IN2P3/LPC) - PRR june’06 6 TTC & clocks ECS I2C : point to point from GLUE to chips Clocks : LVDS – LAL delay chips – Converted to CMOS close to chips L0 Ch B I2C RST

7. Rémi CORNAT (IN2P3/LPC) - PRR june’06 7 ECS Same as ECAL FE board (SPECS, CROC, GLUE) LPC made I2C interface – Used on L0DU & VALIDATION board – ACK check – 8b reg. addressed according to their position into the frame Reg. bank loaded in 1 frame (SW opt.)

8. Rémi CORNAT (IN2P3/LPC) - PRR june’06 8 Power supply Use of -3.3 and 3.3 V only – Not compatible with ECAL/HCAL FE boards -3.3V, 1.5 and 2.5 V made with LHC regulators SEL sensitive components are protected with self switch- off current limiters – Switch with feed back acting as « delatchers » – Partitions of components -51 A / board (ECAL - 5V) +3.3 D5 A / board (ECAL 3.3V) +3.3 D +3.3 A (ECAL +5V) +3.3 A +5 Vfree1Aux for PS CROC

9. Rémi CORNAT (IN2P3/LPC) - PRR june’06 9 Switch characteristics Current limiter – (2A : MAX869, 1.2A : MAX890, – 0.5A : MAX891,…) 2.7 to 5.5 V Switch resistance : 90 m  typ.@3V Programmable current limit (external resistor) – Minimum limit is 0.2*I max (240 mA for MAX890) Fault indicator Enable input (forced switch off is possible) Thermal shutdown MAX869L was tested at GANIL by LAL SN74LVC10 tested by ATLAS Test circuit 74LVC010

10. Rémi CORNAT (IN2P3/LPC) - PRR june’06 FE pga AX1000 Digital processing

11. Rémi CORNAT (IN2P3/LPC) - PRR june’06 11 FEpga Fe_PGA ‘S’ version – AX1000 pga Pipe-lines (ECAL vs PS, SPD vs PS) Tests RAMS (injection & acquisition) ECS (3 banks of resp. 10, 2*34 8b reg. + RAMs) LAL L0 readout ECS interfaces are LPC made

12. Rémi CORNAT (IN2P3/LPC) - PRR june’06 12 Digital processing 8 bits parameters Optimized operators sizes 4 pipe-line steps Offset  [0..255] Gain = 1+ G/512, G  [0..255] Alpha = A/512, A  [0..255] Trigger threshold  [0..255]

13. Rémi CORNAT (IN2P3/LPC) - PRR june’06 13 General architecture ACQ RAM

14. Rémi CORNAT (IN2P3/LPC) - PRR june’06 14 Hamming For parameters registers load_ecs 22 bits words – 16 data bits – 5 hamming bits – 1 global parity bit – Loaded by 8 bits slices from I2C 1 bit error correction 2 bits error detection Decoder shared among 12 22b registers – Cyclic check and correction using a counter

15. Rémi CORNAT (IN2P3/LPC) - PRR june’06 15 P&R results Worst case : 56 MHz Best case : slack > 300 ps Cells : 53%, RAM : 70%, IO : 50% Back annotated simulations – Entry point : I2C

16. Rémi CORNAT (IN2P3/LPC) - PRR june’06 Trigger part

17. Rémi CORNAT (IN2P3/LPC) - PRR june’06 17 L0 trigger Link ECAL to PS/SPD Trigger data = 1b/ch

18. Rémi CORNAT (IN2P3/LPC) - PRR june’06 18 Overview : trigger functions Interconnection between : – SPD and PS (boards corresponding to the same cells) : 24m serial LVDS – Adjacent PS board (T/B : lvcmos 40MHz, R/L : serial LVDS) – ECAL and PS (boards corresponding to the same cells) : serial LVDS – PS and ECAL validation board : serial LVDS – PS and SPD control board (multiplicity) : serial LVDS Synchronization : compensate latencies Cells mapping issue : geographic algorithms 2x2 cluster search algorithm for SPD an PS trigger bits

19. Rémi CORNAT (IN2P3/LPC) - PRR june’06 19 Trigger task Two cluster addresses sent by ECAL – One per half PS FE Board SPD data deserilization – Received in FE PGAs : sent to DAQ – Centralized into TRIG PGA Neighbours algorithm – Transmission between boards – Simple multiplexor… – Need one Tclk Algorithm validated (Q1’01 prototype) SPD Multiplicity – Adder tree Data synchronization – Many pipe-lines…

20. Rémi CORNAT (IN2P3/LPC) - PRR june’06 20 Timing model 6 pipe-line length to set

21. Rémi CORNAT (IN2P3/LPC) - PRR june’06 21 P&R results Worst case : 52 MHz Best case : slack > 55 ps Cells : 38%, RAM : 69%, IO : 90% P&R : routing resources usage close to a limit (uncertain P&R result) – Routing is critical – Frozen pin positions (PCB) – Large buses (128b typ) to connect mapping steps, pipe-lines, RAMS, etc… – 5% more nets lead to 20% loss in max. frequency But : current version is ok and seem to be final

22. Rémi CORNAT (IN2P3/LPC) - PRR june’06 Clock and timing

23. Rémi CORNAT (IN2P3/LPC) - PRR june’06 23 Logical clock tree Clk taken from the backplane No LVDS RT fan-out found… – Delay chips and LV048 – Multidrop LVDS (Up to 2*4 LVDS buffers per branch) Tree trunk and branches are LVDS Tree leaves are LVTTL Delay chips allow to set – VFE (start of analogue integration time) – VFERST (phase of VFE rst signal) – ADC (analogue signal sampling time) – ADC’ (ADC data sampling time into FE_PGAs) – Sampling times of serial LVDS data (SPD, ECAL, TOP)

24. Rémi CORNAT (IN2P3/LPC) - PRR june’06 24 Clock inside PGAs Use of PLL Dedicated pins to use hardwired clock trees Clock regions to optimize best case timing slack (TRIG) SCL ECAL

25. Rémi CORNAT (IN2P3/LPC) - PRR june’06 25 Clock model P0 Fe_PGA

26. Rémi CORNAT (IN2P3/LPC) - PRR june’06 26 Clock distribution (schematics) 4*16 ADCs Global clk 8 FE 1 TRIG 1 SEQ 1 GLUE 4 serializers SPD in FEpga VFE ADC in FEpga Inputs of TRIGpga

27. Rémi CORNAT (IN2P3/LPC) - PRR june’06 SEL & SEU protection

28. Rémi CORNAT (IN2P3/LPC) - PRR june’06 28 Radiation test of the Preshower electronics Have been tested at Ganil in April 2003 – Front-End electronic ADC (AD9203): 4 chips Operational Amplifier (AD8132): 4 chips – Very-Front-End electronic New version of the ASIC integrator: 2 chips with 1 complete channel each Active PMT Base (AB): 2 basis with 2 HV transistors each No cumulated dose effects – 26 krad for AB, ASIC and OA – 52 krad for ADC Some SEL observed for ADC – Not destructive The 4 ADC have been tested getting back to laboratory – They all work perfectly Current in the ADC increased “only” by a factor 3 to 4 – Holding the power supply voltage in the required range – Estimation : 10 SEL per year – Use of delatchers No SEL for AB, ASIC and OA

29. Rémi CORNAT (IN2P3/LPC) - PRR june’06 29 Triple voting Antifuse PGA (FE), RT flash PGA (TRIG, SEQ, GLUE) Triple voting technique : – Used on control bits and FSM state register – Used on RAM address counters – Hamming counters developed (HDL) – Error bits are summarized (logical OR)

30. Rémi CORNAT (IN2P3/LPC) - PRR june’06 30 EDAC Hamming coding 22 bits words – 16 data bits – 5 hamming bits – 1 global parity bit 1 bit error correction 2 bits error detection Decoder can be shared with many registers – Cyclic check and correction using a counter Saves a lot of flip-flops Needs combinational logic Used for alg. param. reg. Synthesis results (4 FE channels) : combseq Ham624230 tv980576

31. Rémi CORNAT (IN2P3/LPC) - PRR june’06 31 Current prototype Main current switch needs more studies ECS error rate too high – Errors seen on SPECS signals before CROC PCB & PGA intensely tested

32. Rémi CORNAT (IN2P3/LPC) - PRR june’06 Annexes

33. Rémi CORNAT (IN2P3/LPC) - PRR june’06 Analogue receiver & digitization

34. Rémi CORNAT (IN2P3/LPC) - PRR june’06 34 Analogue receiver & ADC Q2’01

35. Rémi CORNAT (IN2P3/LPC) - PRR june’06 35 Prototype Constraints – 1 cm height per channel 64 channels/32 cm – EMC Noise σ=0,8 mV lowered to 0,4 mV PCB hierarchical block – CMS 0805 – AD9203 – Compact placement – Ground plane – Signal diff. pairs – Diff. clock

36. Rémi CORNAT (IN2P3/LPC) - PRR june’06 36 New analogue module Refined component placement Compatible for both ADC multiplexing and direct connection to Fe_PGA Optimized differential signal traces Q4’03