1. The digital system design and Verilog Members: r92943089 劉致元 r92943090 羅棠年 r92943097 賴宥任

2. outline ► Introduction ► Description style ► Modeling ► Example and simulation ► Conclusion

3. Advance in Verilog ► Easy to design directly for complex systems ► Model description by Verilog  Easy to modify  Enable automatic synthesis ► Allow architectural tradeoffs with short turnaround ► Reduce time to design capture ► Short the design verification loop

4. The characteristic of Verilog ► Have high-level language constructs to describe the functionality and connectivity of the circuit ► Can describe a design at some level of abstraction: behavioral, RTL, Gate-level, Switch ► Can describe functionality as well as timing ► Can be used to document the complete system design tasks: testing, simulation ► Comprehensive and easy to learn

5. The convenient of Verilog ► Hardware description language ► Mixed level modeling  Behavioral ► Algorithmic ► Register transfer  Structural ► Gate ► Switch ► Single language for design and simulation ► Built-in primitives and logic functions ► User-defined primitives ► Built-in data types ► High-level programming constructs Concept Design HDL Simulation Concept O.K.? Synthesis & Test Gate-level simulation Implementation O.K?

6. Traditional VLSI Design Flow System Specification Functional/ Architecture Design Logic Synthesis Circuit Design Functional simulation Logic simulation Circuit analysis Behavior representation HDL description gate-level representation Switch-level representation

7. Hierarchy description style ► Direct instantiation and connection of models from a separate calling model  Form the structural hierarchy of a design ► A model may be declared anywhere in a design relative to where it is called ► Signals in the higher “ calling ” model are connected to signals in the lower “ called ” model by either:  Named association  Positional association

8. Lexical conventions ► Verilog is a free-format language – like C ► White space (blank, tab, newline) can be used freely ► Verilog is a case-sensitive language ► Identifiers  User-provided names for Verilog objects in the descriptions  Legal characters are “ a-z ”, “ A-Z ”, “ 0-9 ”, “ _ ” and “ $ ” ► First character has to be a letter or an “ _ ”  Example: Count, _ R2D2, five$ ► Keywords  Predefined identifiers to define the language constructs  All keywords are used as identifiers  Cannot be used as identifiers  Example: initial, assign, module

9. Lexical conventions ► Comments: two forms /*First form: can extend over many line*/ //second form: ends at the end of this line ► Strings  Enclosed in double quotes and must be specified in one line ► “ sequence of characters ”  Accept C-liked escape character ► \n = newline ► \t = tab ► \\ = backslash ► \ ” = quote mark ( “ ) ► % = % sign

10. Register types ► Reg: any size, unsigned ► Integer: 32-bit signed (2 ’ s complement) ► Time: 64-bit unsigned ► Real, realtime: 64-bit real number  Defaults to an initial value of 0 ► Example: reg CNT; reg [31:0] SAT; integer A,B,C; //32-bit real SWING; realtime CURR_TIME; time EVENT;

11. parameters types ► Is a Constant ► Example: parameter LINE_LENGTH = 132,ZLL_X_S = 16 ’ b0 parameter BIT = 1, BYTE = 8, PI = 3.14; parameter SROBE_DELAY = (BYTE+BIT)/2 parameter TQ_FILE = “ /home/fds/test/add.tq ” ; ► Common usage  Specify delays and widths

12. Gates model ► The following gates are built-in types in the simulator ► And, nand, nor, or, xor, xnor  First terminal is output, followed by inputs and a1 (out1, in1, in2); nand a2 (out2, in21, in22, in23, in24); ► buf, not  One or more outputs first, followed by one input not N1 (OUT1, INA, CTRLA); buf B1 (BO1, BIN); ► bufif0, bufif1, notif0, notif1: three-state drivers  Output terminal first, then input, then control bufif1 BF1 (OUTA, INA, CTRLA); ► Pullup, pulldown  Put 1 or 0 on all terminals pullup PUP(PWRA, PWRB, PWRC); ► Instance names are optional ex: not (QBAR, Q)

13. Data-flow model ► Models behavior of combinational logic ► Example: wire [3:0] Z, PRESET, CLEAR; assign Z = PRESET & CLEAR; wire COUNT, CIN wire [3:0] SUM,A,B; assign {COUT, SUM} = A+B+CIN ► Left-hand side (target) expression can be a:  Single net (ex: Z)  Part-select (ex:SUM[2:0])  Bit-select (ex: Z[1])  Concatenation of both (ex: {COUT, SUM[3:0]}) ► Expression on right-hand side is evaluated whenever any operand value changes

14. Behavioral model ► Procedural blocks:  Initial block: executes only once  Always block: executes in a loop ► Block execution is triggered based on user-specified conditions  Always @ (posedge clk) … ► All procedural blocks are automatically activated at time 0 ► All procedural blocks are executed concurrently ► Reg. is the main data type that is manipulated within a procedural block  It holds its value until assigned a new value

15. outline ► Introduction ► Description style ► Modeling ► Example and simulation ► Conclusion

16. BAR BAR (50): Apple (40): A slot machine ( 拉霸 ) Watermelon (30): Banana (25): Lemon (20): Orange (15): Guava (10): Cherry (5): Strawberry (2): Nine different type of patterns Win if three patterns are the same Different probability and indemnity between patterns

17.  Game control Coin : Money will you gamble Start : Start the game Return : Money you win Sum : Money in the machine temp=outData[7] ^ outData[9]; outData={outData[8:0],temp};  Random number generator temp=outData[5] ^ outData[8]; outData={outData[8:0],temp}; temp=outData[3] ^ outData[6]; outData={outData[8:0],temp};

18. parameter[3:0] BAR=4'b0001, apple=4'b0010, watermelon=4'b0011, banana=4'b0100, lemon=4'b0101, orange=4'b0110, guava=4'b0111, cherry=4'b1000, strawberry=4'b1001; if(inData<=20) outPattern=BAR; else if(inData<=44) outPattern=apple; else if(inData<=79) outPattern=watermelon; else if(inData<=119) outPattern=banana; else if(inData<=169) outPattern=lemon; else if(inData<=234) outPattern=orange; else if(inData<=334) outPattern=guava; else if(inData<=524) outPattern=cherry; else if(inData<=1024) outPattern=strawberry; Define the pattern into binary code Define the output pattern

19. 4'b0001: return={1'b0,coin[6:0],5'b00000} //return=coin multiply 50 +{2'b00,coin[6:0],4'b0000} +{5'b00000,coin[6:0],1'b0}; 4'b0010:return={1'b0,coin[6:0],5'b00000} //return=coin multiply 40 +{3'b000,coin[6:0],3'b000} +{5'b00000,coin[6:0],1'b0}; 4'b0011:return={1'b0,coin[6:0],5'b00000} //return=coin multiply 30 -{5'b00000,coin[6:0],1'b0}; 4'b0100:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 25 +{3'b000,coin[6:0],3'b000} +{6'b000000,coin[6:0]}; 4'b0101:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 20 +{4'b0000,coin[6:0],2'b00}; 4'b0110:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 15 -{6'b000000,coin[6:0]}; 4'b0111:return={3'b000,coin[6:0],3'b000} //return=coin multiply 10 +{5'b00000,coin[6:0],1'b0}; 4'b1000:return={4'b0000,coin[6:0],2'b00} //return=coin multiply 5 +{6'b000000,coin[6:0]}; 4'b1001:return={5'b00000,coin[6:0],1'b0}; //return=coin multiply 2  Use shift register to replace the multiplier A*50=A*32+A*16+A*2

22. Vending machine Seven kind of thing in vending machine Four type of coin can use : 1, 5, 10, 50 Only can buy one goods at the same time  Vendor control Coin : Money you put in Button : What to buy Amount : Money you have Refund : Money to refund

23. while(coin>=50) begin coin=coin-50; out50=out50+1; end while(coin>=10) begin coin=coin-10; out10=out10+1; end while(coin>=5) begin coin=coin-5; out5=out5+1; end while(coin>=1) begin coin=coin-1; out1=out1+1; end amount=0; end  Refund the money counter1=counter1+in1; counter5=counter5+in5; counter10=counter10+in10; counter50=counter50+in50; amount=amount+in1+in5*5+in10*10+in50*50;  Put in coin

28. Conclusion ► Easy to design directly for complex systems ► Comprehensive and easy to learn ► Allow architectural tradeoffs with short turnaround

29. Thank you