2. Exam 2 Review Two’s Complement Arithmetic Ripple carry ALU logic and performance Look-ahead techniques Basic multiplication and division ( non- restoring) algorithms IEEE 754 floating point standard (definition provided) Write a sequence of register transfers to implement a given instruction for MIPS Given a set of Register Transfers, design the control needed for some component

3. S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S State Register Transfers

4. Next State Function with a Sequencer 16 Control Lines ROM PLA STATE Adder 1 Addr Select logic Op(5 –0) AddrCtl Looks like a Computer !

5. Microprogramming Define a symbolic set of microinstructions used to implement each instruction

6. Microprogramming Define a symbolic set of microinstructions used to implement each instruction The microassembler will check for inconsistencies and convert to binary code

7. Microprogramming Define a symbolic set of microinstructions used to implement each instruction The microassembler will check for inconsistencies and convert to binary code Define independent fields to determine datapath control signals that must be asserted

8. Microprogramming Define a symbolic set of microinstructions used to implement each instruction The microassembler will check for inconsistencies and convert to binary code Define independent fields to determine datapath control signals that must be asserted Define a field to determine the next state

9. Microinstruction Design Label Label controls microcode sequencing Location of entry points Used for sequencing Value can be any string Note: A numeric last character is special for dispatching

10. IR MDR ALU Control

11. Microinstruction Design ALU Label control ALU control Add Subt Func – Use funct field of Op to define operation

12. Microinstruction Design ALU Label control SRC1 SRC2 ALU control Add Subt Func – Use funct field of Op to define operation SRC1 # Select first ALU input PC A SRC2 # Select second ALU input B 4 Extend # sign extended (imm16) Extshft # shift left 2 [sign extended (imm16)]

13. IR MDR Register Control

14. Microinstruction Design ALU Register Label control SRC1 SRC2 control Register control Read# Read Reg(rs) into A, Reg(rt) into B Write ALU# Write ALUOut into Reg(rd) Write MDR# Write MDR into Reg(rt)

15. IR MDR Memory Control

16. Microinstruction Design ALU Register Label control SRC1 SRC2 control Memory Memory Read PC# Read M[PC] into IR ( and MDR) Read ALU# Read M[ALUOut] into MDR Write ALU # Write B into M[ALUOut]

17. IR MDR PCWrite Control

18. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control PCWrite control ALU # Load ALU result into PC ALUOut-cond # If Zero = 1, load ALUOut into PC Jump # Load jump address into PC

19. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Sequencing Seq# Go to next microinstruction in sequence Fetch# Go to microinstruction with Label “Fetch” Dispatch i# Dispatch with ROM i

20. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Sequencing Seq# Go to next microinstruction in sequence Fetch# Go to microinstruction with Label “Fetch” Dispatch i# Dispatch with ROM i See Summary Of Microcode Fields page C-29

21. Basic steps all instructions execute 1.Access the Instruction from Memory 2.Decode Instruction and Access the Data from Registers 3. Perform the Instruction 4. Write the Result

22. S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S S2 A + sign_ext(IR[15-0]) ALUOut, ‘LW’S3 + ‘SW’S5 S S3 M[ ALUOut] MDR, S4 S S4 MDR R[ IR[20-16]], S0 S S5 B M[ ALUOut], S0 S S6 A op B ALUOut, S7 S S7 ALUOut R[IR[15-11]], S0 S S8 Zero PC + Zero ALUOut PC, S0 S S9 PC[31-28] : shlt2(IR[25-0]) PC, S0 S State Register Transfers

23. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch

24. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add

25. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4

26. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC

27. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU

28. S0 M[PC] IR, PC + 4 PC,S1 S State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq

29. State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S

30. State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S

31. State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S

32. State Register Transfers ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S Dispatch 1 Op Code Label lw or swMem1 R – typeRformat1 beqBEQ1 jJUMP1

33. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1

34. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2

35. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch

36. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing lw rt, imm16 (rs) or sw rt, imm16 ( rs) M[ R[rs] + sign_ext(imm16) ] R[rt] R[rt] M[ R[rs] + sign_ext(imm16) ] Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch

37. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1 op rd, rs, rt R – Arithmetic – Logic Instruction R[rs] op R[rt] R [rd]

38. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1 Func A B Seq op rd, rs, rt R – Arithmetic – Logic Instruction R[rs] op R[rt] R [rd]

39. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Rfmat1 Func A B Seq Write ALU Fetch op rd, rs, rt R – Arithmetic – Logic Instruction R[rs] op R[rt] R [rd]

40. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1 beq rs, rt, imm16 I -type Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC Zero =1 iff rs - rt = 0

41. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1 Subt A B beq rs, rt, imm16 I -type Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC Zero =1 iff rs - rt = 0

42. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 BEQ1 Subt A B ALUOut-con Fetch beq rs, rt, imm16 I -type Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC Zero =1 iff rs - rt = 0

43. ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 JUMP1 Jump Addr Fetch j Label go to Label

44. Microinstruction Design ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch Rfmat1 Func A B Seq Write ALU Fetch BEQ1 Subt A B ALUOut-con Fetch JUMP1 Jump Addr Fetch

45. Each field in the microinstruction implies a set of control signals to be asserted. See fig C.21 p.C-29 Implementing the microprogram

46. Each field in the microinstruction implies a set of control signals to be asserted. See fig C.21 p.C-29 If a field that affects a state (memory) is blank, then no control signal should be active. Implementing the microprogram

47. Each field in the microinstruction implies a set of control signals to be asserted. See fig C.21 p.C-29 If a field that affects a state (memory) is blank, then no control signal should be active. If a field that affects a mux or ALU operation is blank, the output is not used, so it is a “don’t care”. Implementing the microprogram

48. Each field in the microinstruction implies a set of control signals to be asserted. See fig C.21 p.C-29 If a field that affects a state (memory) is blank, then no control signal should be active. If a field that affects a mux or ALU operation is blank, the output is not used, so it is a “don’t care”. The microcode assembler 1. Converts the symbolic fields to a truth table for the control signals [ microcode ] 2. Resolves labels to addresses 3. Builds the Dispatch ROM code Implementing the microprogram

49. Microprogram Assembler Microcode ROM Fabrication Control ROM

50. 16 Control Lines Control ROM [Microcode] Micro Counter Adder 1 Addr Select logic Op(5 –0) AddrCtl Contains Dispatch ROM 1 Dispatch ROM 2

51. addi – Add Immediate addi $s1, $s2, 100 # $s1 = $s2 + 100 8 rs rt imm ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 ADDI1 Add ? ? Expand Dispatch 1

52. addi – Add Immediate addi $s1, $s2, 100 # $s1 = $s2 + 100 8 rs rt imm ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 ADDI1 Add A Extend Seq

53. addi – Add Immediate addi $s1, $s2, 100 # $s1 = $s2 + 100 8 rs rt imm ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 ADDI1 Add A Extend Seq ? Write ALU uses rd field !

54. addi – Add Immediate addi $s1, $s2, 100 # $s1 = $s2 + 100 8 rs rt imm ALU Register PCWrite Label control SRC1 SRC2 control Memory control Sequencing Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 ADDI1 Add A Extend Seq Write ALU rt Fetch Write ALU uses rd field ! Define: Write ALU rt = Write Reg[rt] with ALUOut

55. Design Tools Register Transfer Language Initial Finite State Microprogram Representation Diagram Sequencing Explicit next- Microprogram Control State Function Counter + Dispatch ROMs Logic Logic Truth Representation Equations Tables Implementation Programable Read – Only Technique Logic Arrays Memory

56. Exceptions are unexpected or error events. Ex: Undefined instruction Arithmetic overflow

57. Exceptions are unexpected or error events. Ex: Undefined instruction Arithmetic overflow EPC: Exception Program Counter A 32 bit register to hold the address of the affected instruction

58. Exceptions are unexpected or error events. Ex: Undefined instruction Arithmetic overflow EPC: Exception Program Counter A 32 bit register to hold the address of the affected instruction Cause: A 32 bit register to record the cause of the exception.( Option is to vector into OS) Undefined instruction = 0 Arithmetic overflow = 1 OS entry point for exception handling = C0000000 hex

59. Undefined instruction Save Address in EPC, Load 0 in Cause, Jump to C0000000 S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 S

60. Undefined instruction Save Address in EPC, Load 0 in Cause, Jump to C0000000 S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 + ‘Other’S10 S S10

61. Undefined instruction Save Address in EPC, Load 0 in Cause, Jump to C0000000 S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 + ‘Other’S10 S S10 PC – 4 EPC,

62. Undefined instruction Save Address in EPC, Load 0 in Cause, Jump to C0000000 S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 + ‘Other’S10 S S10 PC – 4 EPC, 0 Cause,

63. Undefined instruction Save Address in EPC, Load 0 in Cause, Jump to C0000000 S0 M[PC] IR, PC + 4 PC,S1 S S1 R[IR[25-21]] A, R[IR[20-16]] B, PC + shlt2[sign_ext(IR[15-0])] ALUOut, (‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9 + ‘Other’S10 S S10 PC – 4 EPC, 0 Cause, C0000000 PC, S0 S