1. 5/7/2004Tomi Mansikkala User guide for SVT/XTRP TX firmware v1.0 XTRP out Control FPGA Tomi: - Introduction - Control bit descriptions - Test Pattern format & rules - Missing features (to be done) Frans: - Test setup - VME user software available to configure the Tx - Test results Appendix: - VME address map - Firmware details

2. 5/7/2004Tomi Mansikkala2 - Sends data from RAM after receiving L1A and buffer number from P2 backplane - 4K word internal RAM where user can load test patterns thru VME (if SRAM is used, 128K words can be loaded) - RAM is divided to four buffers, each buffer is 1024 words deep SVT/XTRP Tx firmware features RAM Test pattern Output FIFO L1A with buffer # data latency Can send out different events for a given buffer Can have delay before sending data - delay word: 12bits counts at CDFCLK (for XTRP) Can have gaps between data words - gap word: 12bits counts at CDFCLK (for XTRP) Can have empty events (not needed for SVT/XTRP) - transmitter doesn’t send out anything on certain L1As Transmitting is disabled by default, needs to be enabled via VME

3. 5/7/2004Tomi Mansikkala3 Block diagram 28bit RAM Output FIFO Data Delay FF SM1SM2 Delay Handler 8bit L1AFIFO 8bit SM2L1AFIFO Enabledata data emptybit SM2L1A readrq ready readrq FIFOempty roboclock CDFCLK roboclock data trailerbit data buffer# ready counterReset CDFL1A + buffer CDFCLK delaybit outputbuffer select enable delay FIFOdatastrobe L1AFIFO readrq FIFO empty FIFOEoE Gapbit compare A>=B counter gapReady Start & reset buffer0 buffer1 buffer2 buffer3 A B 4096 1024 CDFCLK enable

4. 5/7/2004Tomi Mansikkala4 Control bits in the user defined test pattern -Test pattern RAM has 4096 28bit words and is divided to 4 buffers 23 data bits + 5 control bits Control bits: 1 st Delay (Delay before sending data out) 2 nd Gap (Gap between data words) 3 rd Empty event (Empty event) 4 th End of event (EoE for TX) 5 th Terminator (user friendly way to mark last event) Control 5bitsData 23bits Buffer 0 Buffer 1 Buffer 2 Buffer 3. 1 st event 2 nd event n th event. 2 nd event n th event 1 st event 4096 RAM

5. 5/7/2004Tomi Mansikkala5 Delay before sending data out: - Set 1 st control bit to high for delay control word - First 12 data bits are used to define delay value - Delay control word has to be in the beginning of each event, if no delay necessary then delay value is set to 0 - Firmware doesn't send delay words out Gap between words: - Set 2 nd control bit to high for gap words - First 12 data bits are used to define gap delay value - Firmware doesn't send gap words out End of event: - Set 4 th control bit to high on the last word of event - Data bits are used for normal data word Control 5bitsData 23bits Buffer 0.......... delay value 4096 RAM data word 1 gap value 1 data word. gap value 1 data word 1 delay bit gap bit EoE bit Delay and gap

6. 5/7/2004Tomi Mansikkala6 Delay before sending data CDFCLK L1A SVT_DS 1,98us Delay value <= 11(decimal): (Minimum L1A to data out delay) 15 * CDFCLK 15 * 132ns = 1.98us Delay value > 11: (Delay value+4) * CDFCLK Example: Delay value is 20 (20+4)*132ns = 31.68us

7. 5/7/2004Tomi Mansikkala7 792ns datastrobe L1A SVT_DS CDFCLK Gap between data words Time of gap word delay: 6 * CDFCLK + gap value (gap value = CDFCLKs) gap value = 0

8. 5/7/2004Tomi Mansikkala8 Control 5bitsData 23bits Buffer 0.......... delay value 4096 RAM data word 1 1 1 Terminator: (a user friendly way to mark last event) - Set 4 th and 5 th control bits to high for the last word - After Terminator next event will be the 1st event in the buffer. Otherwise, continue to next event. Empty event: - Set 3 rd control bit to high on the events first word - Data bits are not sent - Firmware doesn't send any data out on this event - not useful for SVT/XTRP - a feature needed for Cluster delay bit EoE bit data word delay value Terminator & empty event 1 data word 1 Terminator bit......... Buffer 1 data not used Empty event bit 1..........

9. 5/7/2004Tomi Mansikkala9 SVT_DS L1A CDFCLK Empty event no strobes = empty event

10. 5/7/2004Tomi Mansikkala10 Control 5bitsData 23bits Buffer 0 Buffer 1 Buffer 2 Buffer 3. 1 st event 2 nd event 14 th event. 2 nd event 1 st event 4096 RAM Test pattern format rules and example Example - Event size 72 words, total 14 events loaded 71 data words (includes EoE) 1 control word (delay) => 1008 words / buffer - Last word in the 14 th event marked with terminator bit 14 th event 1 st event.. 0 : 080001F ; 1 : 0000001 ; 2 : 0000002 ; 3 : 0000003 ; 4 : 0000004 ; 5 : 100000A ; 6 : 0000005 ; 7 : 0000006 ; 8 : 0000007 ; 9 : 100002B ; 10 : 0000008 ;. 70 : 0000070 ; 71 : C400000 ; One event: Test pattern format (user has to follow) -Beginning of each event has to start from the same RAM location for all buffers -First word in each event has to be either delay word or empty event word -All buffers should have same number of valid events loaded. Last word on last event should be marked with terminator bit -Need at least 2 data words first before gap word(s) can be used gap word delay word EoE + terminator word

11. 5/7/2004Tomi Mansikkala11 Control 5bitsData 23bits Buffer 0 Buffer 1 Buffer 2 Buffer 3. 1 st event 2 nd event 14 th event. 2 nd event 1 st event 4096 RAM Test pattern read back from RAM 14 th event 1 st event.. Highest two read address bits of the RAM are controlled by L1A buffer number when Tx is enabled (to naturally divide the RAM into for four buffers)  - RAM read back should only be done when the Tx is disabled - Outgoing events follow L1A buffer number order Example L1A order: L1A buffer 0  L1A buffer 1  L1A buffer 0  L1A buffer 2 … Outgoing data order: 1 st event from buffer 0  2 nd event from buffer 1  3 rd event from buffer 0  4 th event from buffer 2 … One other way is to stamp buffer bits on data word on the fly for a given L1A … and have events sent out in the same order as loaded. Can implement in next version if desired. 4 th event 1 st 3 rd 2 nd 4 th 3 rd event

12. 5/7/2004Tomi Mansikkala12 Missing features (to be done next) - Current version is for XTRP, the clock is CDFCLK. For SVT data, different clock will be used - Switch (via VME) to either pass thru real SVT/XTRP input or send fake data - Actual Bunch Counter value stamped in the outgoing EOE word for each event (needed by SVT group)

13. 5/7/2004Frans Marjamaa13 Test setup SVT / XTRP TX XTRP RX -Test setup in the lower crate in b0 test stand room -TS calibration setup readout rate 4 kHz -Myron mode L1A Buffer# Slink Output DAQ Input DAQ Output DAQ

14. 5/7/2004Frans Marjamaa14 Test software -Separate (standalone) software for creating a test pattern files -Text file can be modified later (change delay value, add gap words…) Current version of the software does not put any gap words in the pattern -Test are run using run control -Also standalone version for loading test pattern to TX RAM is available for others to use. It can be found in the online machines (~marjamaa/pulsar/utils/loadsvt/) SVT / XTRP TX VME BUS Crate CPU Text file

15. 5/7/2004Frans Marjamaa15 Test pattern example Delay EOE Delay EOE + Terminator

16. 5/7/2004Frans Marjamaa16 -Tested using variable event sizes (14 different events for every buffer) -Long test, run ~80M events with 4kHz readout rate -Different delay and gap values also tested and checked on logic analyzer -All tests passed error free! Test results

17. 5/7/2004Tomi Mansikkala17 Appendix - VME address map - Delay handler block diagram - RAM to FIFO SM - TX FIFO out SM - Tx enable/disable feature block diagram

18. 5/7/2004Tomi Mansikkala18 TX XTRP Control FPGA Address Action 32-bit Hex YY000000 (R) Firmware version YY000004 (W) Reset YY000024 (R/W) Enable TX (bit 0: high=enabled, low=disabled) YY600000 (W) RAM write YY600004 (W) Reset RAM address counter YY600008 (W) Advance RAM address counter YY60000C (R) RAM read YY100000 – YY10007C (R) IDPROM YY = VME address bits 31..24. These bits are not used by firmware Format: Firmware ID + Date + Version number 8-bits 20-bits 4-bits Current version: Control SVT TX 05/06/04 Hex: A6405060 Firmware version

19. 5/7/2004Tomi Mansikkala19 SVT/XTRP: delayhandler component FF compare counter FF compare counter FF compare counter FF compare counter ready readyB2 readyB3readyB0readyB1 Demux Delay in Enable delay Select input buffer Delay in Enable delay B0 Delay inEnable delay B1 Delay in Enable delay B2 Delay in Enable delay B3 Reset when B0 & L1A Reset when B1 & L1A Reset when B2 & L1A Reset when B3 & L1A B0 = (((not bufferbit(0)) and (not bufferbit(1)) and ReadyB0) or B1 = (bufferbit(0) and (not bufferbit(1)) and ReadyB1) or B2 = ((not bufferbit(0)) and bufferbit(1) and ReadyB2) or B3 = (bufferbit(0) and bufferbit(1) and ReadyB3)); roboclock CDFCLK Select output buffer FF

20. 5/7/2004Tomi Mansikkala20 WaitL1A readBack2 readBack1 readBack0 searchBoE writeEoE checkData waitData Change3B waitData Change2B waitData Change1B waitData Delay2 waitData Delay1 enable Delay readFirst WaitData Change3 WaitData Change2 WaitData Change1 [L1AFIFOEmpty = ‘1’] [L1AFIFOEmpty=‘0’] L1AFIFOrdreq = ‘1’ [else] [DelayBit=‘1’] enableDelay = ‘1’ enableAddrCounter=‘1’ enableDelay = ‘0’ FIFOdatastrobe = ‘1’ [else] [DelayBit=‘1’ or EmptyBit=‘1’ chgRAMaddrCountDir = ‘0’ enableAddr Counter=‘0’ [Trailer=‘0’ and Terminator=‘0’] [emptyBit=‘1’] emptyEvent = ‘1’ enableAddrCounter=‘1’ FIFOdatastrobe = ‘0’ clearAddrCounter=‘1’ FIFOdatastrobe=‘0’ FIFOdatastrobe = ‘0’ SVT/XTRP: TXRAMtoFIFOInterface clearAddr Counter=‘0 ’ FIFOdatastrobe = ‘1’ [Trailer=‘1’ and Terminator=‘0’] emptyEvent=‘0’ [else] enableAddr Counter=‘0’ chgRAMaddr CountDir=‘1’

21. 5/7/2004Tomi Mansikkala21 CheckData CheckGap Ready Delay2Gap [SM2L1AFIFOEmpty=‘0’] SML1AFIFOrdreq = ‘1’ SML1AFIFOrdreq = ‘0’ enableData = ‘0’ [FIFOEoE=‘1’] readFIFO = ‘0’ enableData = ‘1’ ResetGapCounter = ‘0’ [GapReady=‘1’ ] EnableGapCounter =‘0’ readFIFO = ‘0’ [FIFOEoE=‘0’ and EmptyEventIn=‘0’ and GapBit=‘0’] readFIFO = ‘0’ enableData = ‘1’ First <= false [SM2L1AFIFOEmpty = ‘1’] [FIFOEmpty=‘0’ and Ready=‘1’] readFIFO = ‘1’ readFIFO = ‘0’ [GapReady=‘0’] SVT/XTRP: TXSTM [else] waitL1A strobeEoE Delay for ready Wait data and delay Delay Data [EmptyEventIn=‘1’] readFIFO = ‘0’ Delay1Gap Null [GapBit=‘1’ and First=False] EnableGapCounter = ‘1’ ResetGapCounter = ‘1’ readFIFO = ‘0’ enableData=‘0’ Delay1st Gap [GapBit=‘1’ and First=True] EnableGapCounter = ‘1’ ResetGapCounter = ‘1’ readFIFO = ‘0’ enableData = ‘1’ First <= false ResetGapCounter = ‘0’ readFIFO=‘0’ enableData=‘0’ SVT DS readFIFO = ‘1’ enableData=‘0’ delayEoE enableData = ‘0’

22. 5/7/2004Tomi Mansikkala22 RAM 10b RAM read address counter 12b RAM read address counter VME bus L1A RAM READ address 12b MUX SM1 clr ena 2bBuffer# Select (enable tx) enaclr 12b L1A & enable tx L1A Dual port RAM Tx enable also selects the control of the two highest bits of RAM read address. User has full control of all read address when Tx is in disabled mode TX enable/disable feature