1. UBI >> Contents Lecture 14 RF link using the eZ430-RF2500 & Interrupts MSP430 Teaching Materials Texas Instruments Incorporated University of Beira Interior (PT) Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos University of Beira Interior, Electromechanical Engineering Department www.msp430.ubi.pt Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt

2. UBI >> Contents 2 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Contents (1/2)  RF Introduction RF Introduction  The application The application  The hardware The hardware  The software The software  Configuration Configuration  Algorithms Algorithms  New challenges New challenges

3. UBI >> Contents 3 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Contents (2/2)  Interrupt Introduction Interrupt Introduction  Interrupt: Processor's Perspective Interrupt: Processor's Perspective  Interrupt Service Routine Interrupt Service Routine  Some Common Questions Some Common Questions  Interrupt Vector Table Interrupt Vector Table  Interrupt Latency Interrupt Latency  Sources of Interrupt Overhead Sources of Interrupt Overhead

4. UBI >> Contents 4 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt RF Introduction (1/3)  This laboratory demonstrates the operation of a small wireless communication application;  The purpose of this laboratory is to send and receive text messages, making use of RF links between the central unit (base unit) and the various peripheral units (remote units).  It is an integrated application, using some peripherals of the MSP430, in particular, the USCIx communication modules;  Additionally, it uses the CC2500 radio transceiver as an interface to external devices;  Even though the application is simple, it is motivating to the user because the IO console allows easy interaction with the system;

5. UBI >> Contents 5 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt  This laboratory has the following objectives:  To demonstrate the importance of software organization as a fundamental part of an embedded systems project: To approach the problem using a top-down approach, applying the necessary abstraction to organize the software into functional layers.  To give an example of the management of a complex project, integrating together more than one functional module: To develop a modular structure so that several functional modules co-exist together within a single software project. RF Introduction (2/3)

6. UBI >> Contents 6 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt RF Introduction (3/3)  This laboratory has the following objectives (continued):  Make use of the wireless communications capability of the MSP430, demonstrating its practical advantages;  Consolidate knowledge acquired during the previous laboratories, namely: From the MSP430 communications interfaces laboratories: –SPI mode to access the transceiver CC2500; –UART mode to interface with the IO console.

7. UBI >> Contents 7 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The application (1/2)  This laboratory establishes communications between various RF units;  The stations are identified by an ID, i.e., the address for presentation to the network. When a station wants to communicate with another station, it must use the address of the target station in the message;  The CC2500 has several ways to communicate, which determine the size of the messages exchanged;  In order to simplify the communication process, fixed- size address and data have been used (maximum message size 64 bytes). This corresponds to the size of the CC2500 FIFO.

8. UBI >> Contents 8 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The application (2/2)  CC2500 packages format:

9. UBI >> Contents 9 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The hardware (1/3)  The CC2500 is a radio frequency transceiver operating in the widely used ISM/SRD (Industrial-Scientific-Medical /Short-Range-Devices) 2.4 GHz frequency band;  It is a low-cost device with low power consumption, designed for consumer electronics applications.

10. UBI >> Contents 10 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The hardware (2/3)  The communications protocol uses very little data formatting. It is up to the user to define the communications protocol that best suits their application and implement their own software;  The CC2500 is a low pin-out device, because it integrates all the radio functions, except the antenna;  This device is not sufficiently independent that it can operate without the aid of a microcontroller;  When coupled to the MSP430, connection is made between: Access to internal registers: SPI interface belongs to the USCIB0 unit; Status pins: GDO0 and GDO2 (P2.6 and P2.7).

11. UBI >> Contents 11 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The hardware (3/3)  CC250 RF transceiver:

12. UBI >> Contents 12 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The software (1/2)  Internal structure:  Structured in layers: Base layer: Hardware abstraction layer. Responsible for separating the higher layers of software from the hardware; Middle SPI layer: Ensures the communication functions for the correct operation of CC2500; UART layer: Provides connection to the PC via RS232; CC2500 layer: Access and control functions controlling the CC2500 (SPI and the GPIO); Application layer: Uses the features offered by layers at a lower level to implement the tasks necessary for the correct operation of the application.

13. UBI >> Contents 13 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt The software (2/2)  Software structure:

14. UBI >> Contents 14 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Configuration (1/3)  Clearly defined start-up of the multiple hardware modules and the various software modules;  Important: The unit’s address needs to be changed during compilation, to allocate a unique address.

15. UBI >> Contents 15 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Configuration (2/3)  Remote station code:  Composed of two interrupt service routines (ISR) and two buffers: Port1 ISR Port2 ISR

16. UBI >> Contents 16 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Configuration (3/3)  Remote station code: Port1 ISR: –Enabled by the GDO0, which causes a L-H transition when it receives a valid Sync_Word; –H-L transition at the end of a message reception; –Received message contents to IO console (RS232). Port2 ISR: Generated when the button is pressed, sending the signal announcing the presence of the remote station; Two buffers used to hold the messages: –Transmit buffer is used to build the message for later transmission; –The receive buffer is used to hold the data read from the CC2500 FIFO after receiving a message.

17. UBI >> Contents 17 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Algorithms (1/2)  Transmission algorithm implemented by Port2 ISR:

18. UBI >> Contents 18 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Algorithms (2/2)  Reception algorithm used by the Port1 ISR in both stations:

19. UBI >> Contents 19 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt New challenges  The messages typed into the IO console for a particular address would be sent by wireless support to the console addressed.  To achieve this objective, it is useful to define a small set of user-defined commands, such as: Address allocation at the local station; Address allocation at the remote station; Sending a message; Neighbourhood screening of possible talking partners; Among others…

20. UBI >> Contents 20 Interrupt Introduction (1/3) WWhen MSP430 processor executes the following code, it will loop forever; QQuestion: How can it execute other codes that handle external events, e.g. I/O, timer? StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL SetupP1 bis.b #001h,&P1DIR ; P1.0 output Mainloop xor.b #001h,&P1OUT ; Toggle P1.0 Wait mov.w #050000,R15 ; Delay to R15 L1 dec.w R15 ; Decrement R15 jnz L1 ; Delay over? jmp Mainloop ; Again

21. UBI >> Contents 21 Interrupt Introduction (2/3)  Option 1:  Put codes that handle external events in your main program  polling ; StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL SetupP1 bis.b #001h,&P1DIR ; P1.0 output Mainloop xor.b #001h,&P1OUT ; Toggle P1.0 Wait mov.w #050000,R15 ; Delay to R15 L1 dec.w R15 ; Decrement R15 jnz L1 ; Delay over? bit.b #B1,&P2IN ; Test bit P2IN jnz ButtonUp ; Jump if not zero bis.b #LED1,&P2OUT ; Turn LED1 on ButtonUp: jmp Mainloop ; Again

22. UBI >> Contents 22 Interrupt Introduction (3/3) OOption 2: KKeep your program unchanged and force the processor to jump to the code handling the external event when that event occurs. RRequirements: MMust know when the event occurs; MMust let the processor know where to jump to execute the handling code; MMust not allow your program know!!  you program must execute as if nothing happens;  Must store and restore your program state. This is called interrupt!

23. UBI >> Contents 23 Interrupt: Processor's Perspective (1/2)  Interrupts are triggered when certain events occur;  Usually done by sending a signal to one of the processor’s IRQ (interrupt request) pins.

24. UBI >> Contents 24 Interrupt: Processor's Perspective (2/2)  An interrupt signal stops processor at the next instruction and the processor saves the address of the next instruction on the stack;  Jumps to a specific interrupt service routine (ISR).  ISR is basically a subroutine to perform operations to handle the interrupt with a RETURN at the end.  It is common to save the register contents onto the stack (saving the state) and restoring them at the end of the ISR (restoring the state).

25. UBI >> Contents 25 Interrupt Service Routine (1/2)  The following shows an example of an ISR: Task CodeISR... MOVE R1, R7 MUL R1, 5 PUSH R1 ADD R1, R2PUSH R2 DIV R1, 2... JCOND ZERO, END;ISR code comes here SUBTRACT R1, R3......POP R2...POP R1 END: MOVE R7, R1RETURN...

26. UBI >> Contents 26 Interrupt Service Routine (2/2)  An ISR is like a subroutine, invoking similar operations;  Subroutine:  Program has total control of when to call and jump to a subroutine.  ISR:  Program is forced by hardware signals to jump to an ISR at an unpredictable time, not by its control.

27. UBI >> Contents 27 Disabling Interrupts  Programs may disable interrupts  In most cases the program can select which interrupts to disable during critical operations and which to keep enabled by writing corresponding values into a special register;  Nonmaskable interrupts cannot be disabled and are used to indicate power failures or serious event.  Certain processors assign priorities to interrupts  Allowing programs to specify a threshold priority;  Only interrupts having higher priorities than the threshold are enabled and the ones below it are disabled.

28. UBI >> Contents 28 Where to Put ISR Code?  Challenges:  Locations of ISRs should be fixed so that the processor can easily find them;  Different ISRs may have different lengths  Hard to track their starting addresses;  Application programs may supply their own ISRs; thus ISR codes may change dynamically.  Possible solutions:  ISR is at a fixed location, e.g., in 8051, the first interrupt pin always causes 8051 to jump to 0x0003;  A table in memory contains addresses of ISR  The table is called interrupt vector table.

29. UBI >> Contents 29 How to Know Who Interrupts?  Simple answer: according to interrupt signal  One interrupt signal corresponds to one ISR;  Difficult problem: same interrupt signal shared by several devices/events  Option 1: inside the corresponding ISR, poll and check these devices/events in turn  Devices are passive;  Option 2: devices/events provide the address of ISRs  Devices are proactive;  Vectored interrupt.

30. UBI >> Contents 30 Some Common Questions  Can a processor be interrupted in the middle of an instruction?  Usually not;  Exceptions: critical hardware failure, long-running instructions (e.g. moving data in memory).  If two interrupts occur at the same time, which ISR does the process do first?  Prioritize the interrupt signals.  Can an interrupt signal interrupt another ISR?  Interrupt nesting usually allowed according to priority;  Some processor may require re-enabling by your ISR.  What happens when an interrupt is signaled while the interrupt is disabled?  Processors usually remember the interrupt signals and jump to the ISR when the interrupt is enabled.

31. UBI >> Contents 31 Interrupt Vector Table Interrupt SourceInterrupt Flag System Interrupt Word AddressPriority Power-up External Reset Watchdog Timer+ Flash key violation PC out-of-range PORIFG RSTIFG WDTIFG KEYV Reset0FFFEh31 (highest) NMI Oscillator Fault Flash memory access violation NMIIFG OFIFG ACCVIFG Non-maskable Non-maskable Non-maskable 0FFFCh30 0FFFAh29 0FFF8h28 0FFF6h27 Watchdog Timer+WDTIFGmaskable0FFF4h26 Timer_A2TACCR0 CCIFGmaskable0FFF2h25 Timer_A2TACCR1 CCIFG TAIFG maskable0FFF0h24 0FFEEh23 0FFECh22 ADC10ADC10IFGmaskable0FFEAh21 USIUSIIFG USISTTIFG maskable0FFE8h20 I/O Port P2 (2)P2IFG.6 P2IFG.7 maskable0FFE6h19 I/O Port P1 (8)P1IFG.0 to P1IFG.7 maskable0FFE4h18 0FFE2h17 0FFE0h16 Unused0FFDEh to 0FFCDh15 - 0

32. UBI >> Contents 32 Interrupt Latency  Interrupt latency is the amount of time taken to respond to an interrupt. It depends on:  Longest period during which the interrupt is disabled;  Time to execute ISRs of higher priority interrupts;  Time for processor to stop current execution, do the necessary ‘bookkeeping’ and start executing the ISR;  Time taken for the ISR to save context and start executing instructions that count as a ‘response’.  Make ISRs short  Factors 2 and 4 are controlled by writing efficient code that are not too long ;  Factor 3 depends on HW, not under software control.

33. UBI >> Contents 33 Sources of Interrupt Overhead  Handler execution time  Interrupt mechanism overhead  Register save/restore  Pipeline-related penalties  Cache-related penalties