1. Dual Chip Wafer Level CSP with Sintering Paste LGA
Catherine Shearer, Ken Holcomb and Michael Matthews
Ormet Circuits, Inc.
Maria Spiteri and Ivan Ellul
STMicroelectronics

2. Overview The state of fan-in WLP
Description of the Lab4MEMS consortium effort
How is the Lab4MEMS program leveraging WLP?
Package concept and process flow
Focus on LGA
Process scheme
Land formation
Interconnect to the die
Interconnection to the outside world
Results and next steps
Summary

3. The State of Fan-In WLP
Fan-in WLP has become well established in the industry
As shown in the Yole chart, fan-in WLP continues to grow briskly
With the fundamentals well established, there is an opportunity to explore new architectures and levels of integration

4. The Lab4MEMS Consortium
Lab4MEMS is an R&D project funded by the EU under ENIAC
Develop key enabling technologies
Piezoelectric and magnetic based devices
Smart MEMS sensors and actuators
Advanced 3D packaging
9 countries participating

5. Focus: Dual Die WLP Package
ASIC and sensor die
Nested face-to-face
Through mold interconnect
Vertical wire bond, or
Stacked wire bump
Extend beyond height of sensor (daughter) die
LGA
Formation material/method
Connection scheme to vertical interconnect
Surface finish

6. Process Flow Overview Land grid array recessed into mold compound
Sintering conductive paste used to form land grid array
Chip to Wafer
Face to Face Interconnection
Wafer Molding
Vertical Wire/Stud bump Connection
Laser drilling and Land Grid Formation
Vertical Wire/Stud bump Exposed
Soldering of lands

7. Vertical Interconnect from Mother Die to Top of Mold Surface

8. Formation of the LGA and Connection to the Vertical Interconnect
Advantages of an LGA vs. a BGA
Shorter interconnect length
Tighter pitch possible
Package height reduction
Problems with plating the package
Complicated process
Expensive
Potential for voids at plating/wire interface
Proposed solution: sintering paste
Adheres to mold compound
Simple deposition
Metallurgical interface to vertical interconnect
Platable and solderable

9. Sintering pastes Copper and tin-alloy particles in a flux mixture
During heating ( C depending on formula) the tin- alloy melts and reacts with copper particles and solderable surfaces
Inert environment required (N2, press, vacuum, reducing)
Pressure not required
Continuous metal joint after thermal process
No remelt
Wide variety of rheologies available
Electrical, thermal and mechanical properties similar to solders
Cu-Sn phases
Compliant TLPS design
Copper particle
Residual alloy bridge

10. Explaining Transient Liquid Phase Sintering (TLPS) Pastes
Unprocessed Paste
Sintered Network After Processing
Bringing us back to LPS – What is it and how best to describe it?
The illustration depicts a Transient Liquid Phase Sintered Paste which is formulated with an fluxing epoxy resin system, a tin-bismuth
alloy and copper particles in the uncured paste. There is a short movie to help understand what happens during the curing of this style of paste.
During cure (When heated or reacted above 140C) the tin-bismuth alloy melts. The tin would rather form an intermetallic with the copper than remain with the bismuth. During the cure profile the tin forms an intermetallic network that sinters the copper powder into a solid network and sinters to any adjacent solder ready surface.
The colors in the picture are:
Black: Polymer network
light Gray: bismuth
Medium gray: tin-copper intermetallic
Dark gray: copper
Proprietary organics, copper and tin alloy particles:
Transient Liquid Phase Sintering (TLPS) 10

11. Sintering Pastes Are Used in a Variety of Applications
Image
Microvia fill
Stenciled Interconnect
Through hole fill
X-Y Traces
Component Attach
Die attach paste (DAP)
TLPS pastes have been used for 20+ years in high reliability, high performance PCB applications

12. Sintering Paste Implementation
Initial design concept posed some implementation challenges
The contact area with the exposed top of the vertical wire was very small
Not all the wires were straight
Concern about the ability of the adhesive bond between the sintering paste and the mold compound to survive SMT
Some of the RDL to the I/O footprint included in the surface print – aggressive for a print design
RDL

13. First Test Vehicle Solution: Laser Ablate the Mold Compound in the RDL + LGA pattern and Fill with Sintering Paste
Creating a laser ablated recessed pattern:
Increases connection area between wire and TLPS paste
Compensates for wires that are not straight
Prevents bridging between the small features
Increases contact area between the paste and mold compound for more robust adhesion
Results in a pattern that is flush with the surface of the mold compound
Au wires
Filled with TLPS paste
laser ablated pattern
TLPS paste

14. Results for the first test vehicle
The RDL + pad pattern could be laser ablated
CO2 laser used to ablate – no effect on the wire
All of the wires became exposed and the contact area was increased
Differential ablation of the polymer and silica resulted in irregular depth and edges
Irregular and insufficient depth resulted in poor sintering of paste
With additional ablation time, good fill and sintering was achieved
Concern about how to mask the RDL portion

15. Plan for the second test vehicle
Move the RDL to the interior of the package
Only the LGA on the surface of the package
Use the stacked bump interconnect rather than a wire
Laser ablate to the deeper dimension
Consider a finish metal on the exposed pad surface X X X X X X X

16. Preparing the laser ablated cavities in the second test vehicle
After grinding, the exposed bump stack surface was ~60µm
Sufficient for a good interconnect
Decision to ablate for the improved mechanical ruggedness
Ablating cavities results in pads flush with the surface of the mold compound
Laser ablation was challenging
Laser energy reflected off of the metal bump stack
Large variation in size of silica filler

17. Creating and planarizing the LGA pattern in the second test vehicle
Sintering paste flood filled into the laser ablated LGA pattern
Surface residue polished off after sintering
Issues:
Some metal particles embedded in mold compound – extensive polishing required
Wafer substantially warped during sintering cycle – difficult to handle for polishing

18. Functional Testing of the Second Test Vehicle
Wafer probed for electrical continuity
Positive results
Cross section reveals good metallurgical connection between the bump stacks and the sintering paste
Sintering paste
Bump stack
Mold compound Si

19. LGA surface finish Sintered paste surface is unfamiliar to assemblers
Some sintering techniques result in a rough surface texture
Reflowed solder paste explored first
Stencil application challenging due to warpage of wafer
Good solder wetting to paste
Electroless plated surfaces currently under investigation
ENIG plating successful
Solder paste stenciled onto sintered paste LGA and reflowed

20. Next Steps
Scribe wafer after bump stack reveal to relieve warpage from sintering operation
Explore variations in the sintering technique to minimize warpage and finished surface roughness
Explore alternative electroless plated finshes: Ag, Sn, ENEPIG
Revisit stencil printing on surface of mold compound
Solder paste printing demonstrates that stencil application is possible with LGA-only design
Revealed bump stack top is sufficient in size to make good electrical connection
Mechanical ruggedness of sintered paste to mold compound bond for SMT needs to be evaluated

21. Summary New dual die fan-in WLP under development
Part of the Lab4MEMS consortium effort
Nested face to face sensor + ASIC
Through mold vias from mother die extended past nested daughter die
LGA vs. BGA
LGA formed from sintering paste
Good electrical interconnection achieved
Implementation strategy under investigation
Laser ablated recesses vs. surface printing
Final surface finishes under investigation