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Let’s look at a normal lw instruction first… 1
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2 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) $6 Memory[8 + contents of $7] PC value: 1000 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![2 Register file addresscontent 6 (00110) (00111) OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) $6 Memory[8 + contents of $7] PC value: Memory addresscontent lw encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_2.jpg "2 Register file addresscontent 6 (00110) (00111) OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) $6 Memory[8 + contents of $7] PC value: Memory addresscontent lw encoding … …")
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3 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1000 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) $6 Memory[8 + contents of $7]
![3 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) $6 Memory[8 + contents of $7]](http://images.slideplayer.com./26/8652725/slides/slide_3.jpg "3 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) $6 Memory[8 + contents of $7]")
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4 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1000 10 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 1, State 0: Fetch load instruction IR Memory(PC) || PC PC + 4 IR contains: 100011-00111-00110-0000000000001000 0 01 See control logic discussion 00
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5 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 00111 10000 10 Load 10000 10 into A register
![5 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load into A register](http://images.slideplayer.com./26/8652725/slides/slide_5.jpg "5 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load into A register")
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6 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 00110 9 10 Load 9 10 into B register
![6 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load 9 10 into B register](http://images.slideplayer.com./26/8652725/slides/slide_6.jpg "6 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load 9 10 into B register")
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7 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Calculate address in case it is needed. (hardware is available, so use ASAP)
![7 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Calculate address in case it is needed.](http://images.slideplayer.com./26/8652725/slides/slide_7.jpg "(hardware is available, so use ASAP).")
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8 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 0 11 See control logic discussion
![8 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 0 11 See control logic discussion](http://images.slideplayer.com./26/8652725/slides/slide_8.jpg "8 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 0 11 See control logic discussion")
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9 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) 10000 10 ‘A’ register is:10000 10 Immediate value is: 8 10 (0000 0000 0000 1000 2 ) Immediate value is padded with leading 0s to get 2 nd 32-bit number 0000 0000 0000 0000 0000 0000 0000 1000 2 8 10
![9 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) ‘A’ register is: Immediate value is: 8 10 ( ) Immediate value is padded with leading 0s to get 2 nd 32-bit number](http://images.slideplayer.com./26/8652725/slides/slide_9.jpg "9 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) ‘A’ register is: Immediate value is: 8 10 ( ) Immediate value is padded with leading 0s to get 2 nd 32-bit number")
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10 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) 1 10 See control logic discussion Cycle 3, State 2: Calculate address ALUOut A + SignExt(IR[15:0]) 10000 10 8 10 10008 10 ALUOut contains address to send to memory
![10 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) 1 10 See control logic discussion Cycle 3, State 2: Calculate address ALUOut A + SignExt(IR[15:0]) ALUOut contains address to send to memory](http://images.slideplayer.com./26/8652725/slides/slide_10.jpg "10 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) 1 10 See control logic discussion Cycle 3, State 2: Calculate address ALUOut A + SignExt(IR[15:0]) ALUOut contains address to send to memory")
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11 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address 10008 10 sent to memory Want to load 70 10 into Memory Data Register 10008 10 Data from memory is 70 10
![11 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address sent to memory Want to load into Memory Data Register Data from memory is 70 10](http://images.slideplayer.com./26/8652725/slides/slide_11.jpg "11 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address sent to memory Want to load into Memory Data Register Data from memory is 70 10")
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12 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] 1 Choose ALUOut to get memory address Put 70 10 in MDR
![12 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] 1 Choose ALUOut to get memory address Put in MDR](http://images.slideplayer.com./26/8652725/slides/slide_12.jpg "12 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] 1 Choose ALUOut to get memory address Put in MDR")
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13 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR 70 10 00110
![13 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR](http://images.slideplayer.com./26/8652725/slides/slide_13.jpg "13 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR")
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14 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR 0 1 6 10 70 10
![14 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR](http://images.slideplayer.com./26/8652725/slides/slide_14.jpg "14 Register file addresscontent 6 (00110) (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR")
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15 Register file addresscontent 6 (00110)9 10 70 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR 0 1 6 10 70 10
![15 Register file addresscontent 6 (00110)9 10 (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR](http://images.slideplayer.com./26/8652725/slides/slide_15.jpg "15 Register file addresscontent 6 (00110)9 10 (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw $6,8($7) Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR")
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Now, let’s revisit lw++ 16
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Recall… lw++ would do the following… –lw++ $6, 8($7) $6 Memory[8 + content of $7] || $7 $7 + 4 Why is this useful? –Assume we wanted to iterate through an array … we might use the following sequence of instructions: lw $t, 0($x) addi $x, $x, 4 –The above 2 instruction sequence (requiring 9 CCs) could be replaced by a single instruction that takes 5 or 6 CCs Now, let’s talk about the hardware to make lw++ work! 17
![Recall… lw++ would do the following… –lw++ $6, 8($7) $6 Memory[8 + content of $7] || $7 $7 + 4 Why is this useful.](http://images.slideplayer.com./26/8652725/slides/slide_17.jpg "–Assume we wanted to iterate through an array … we might use the following sequence of instructions: lw $t, 0($x) addi $x, $x, 4 –The above 2 instruction sequence (requiring 9 CCs) could be replaced by a single instruction that takes 5 or 6 CCs Now, let’s talk about the hardware to make lw++ work. 17.")
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18 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 11111100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) $6 Memory[8 + contents of $7] $7 $7 + 4 PC value: 1000 10 Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 Opcode must change! (Assume 111111 is available.)
![18 Register file addresscontent 6 (00110) (00111) OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) $6 Memory[8 + contents of $7] $7 $7 + 4 PC value: Memory addresscontent lw++ encoding … … Opcode must change.](http://images.slideplayer.com./26/8652725/slides/slide_18.jpg "(Assume is available.).")
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19 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1000 10 This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 11111100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) $6 Memory[8 + contents of $7] $7 $7 + 4 Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![19 Register file addresscontent 6 (00110) (00111) PC value: This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) $6 Memory[8 + contents of $7] $7 $7 + 4 Memory addresscontent lw++ encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_19.jpg "19 Register file addresscontent 6 (00110) (00111) PC value: This sequence of 1s and 0s OpcodeSource register Destination register Immediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) $6 Memory[8 + contents of $7] $7 $7 + 4 Memory addresscontent lw++ encoding … …")
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20 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1000 10 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) Cycle 1, State 0: Fetch load instruction IR Memory(PC) || PC PC + 4 IR contains: 111111-00111-00110-0000000000001000 0 01 See control logic discussion 00 Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
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21 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 00111 10000 10 Load 10000 10 into A register Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![21 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load into A register Same as normal lw Memory addresscontent lw++ encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_21.jpg "21 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load into A register Same as normal lw Memory addresscontent lw++ encoding … …")
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22 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) 00110 9 10 Load 9 10 into B register Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![22 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load 9 10 into B register Same as normal lw Memory addresscontent lw++ encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_22.jpg "22 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Load 9 10 into B register Same as normal lw Memory addresscontent lw++ encoding … …")
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23 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Calculate address in case it is needed. (hardware is available, so use ASAP) Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![23 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 2, State 1: Decode instruction A RF[25:21] || B RF[20:16] || ALUOut PC + SignExt(IR[15:0]) Calculate address in case it is needed.](http://images.slideplayer.com./26/8652725/slides/slide_23.jpg "(hardware is available, so use ASAP) Same as normal lw Memory addresscontent lw++ encoding … …")
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24 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 address 1000 10 : lw++ $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) 10000 10 A register is:10000 10 Immediate value is: 8 10 (0000 0000 0000 1000 2 ) Immediate value is padded with leading 0s to get 2 nd 32-bit number 0000 0000 0000 0000 0000 0000 0000 1000 2 8 10 10008 10 Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![24 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) A register is: Immediate value is: 8 10 ( ) Immediate value is padded with leading 0s to get 2 nd 32-bit number Same as normal lw Memory addresscontent lw++ encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_24.jpg "24 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits address : lw++ $6,8($7) Cycle 3, State 2 Calculate address ALUOut A + SignExt(IR[15:0]) A register is: Immediate value is: 8 10 ( ) Immediate value is padded with leading 0s to get 2 nd 32-bit number Same as normal lw Memory addresscontent lw++ encoding … …")
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25 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address 10008 10 sent to memory Want to load 70 10 into Memory Data Register 10008 10 Data from memory is 70 10 address 1000 10 : lw++ $6,8($7) Part 1: Same as normal lw Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10
![25 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address sent to memory Want to load into Memory Data Register Data from memory is address : lw++ $6,8($7) Part 1: Same as normal lw Memory addresscontent lw++ encoding … …](http://images.slideplayer.com./26/8652725/slides/slide_25.jpg "25 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] Address sent to memory Want to load into Memory Data Register Data from memory is address : lw++ $6,8($7) Part 1: Same as normal lw Memory addresscontent lw++ encoding … …")
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26 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address 1000 10 : lw++ $6,8($7) Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 Part 2: NEW! 10000 10 8 10 Content of A and B registers still has not changed Idea: Use idle ALU to update the value in register A (i.e. $7) while the memory access occurs.
![26 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address : lw++ $6,8($7) Memory addresscontent lw++ encoding … … Part 2: NEW.](http://images.slideplayer.com./26/8652725/slides/slide_26.jpg "Content of A and B registers still has not changed Idea: Use idle ALU to update the value in register A (i.e. $7) while the memory access occurs..")
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27 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address 1000 10 : lw++ $6,8($7) Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 Part 2: NEW! To make this work, need to assert other control signals in State 3 to do an add operation: ALUSrcA = 1 # select A input ALUSrcB = 01# select 4 input ALUOp = 00# perform add MemRead IorD = 1 ALUSrcA = 1 ALUSrcB = 01 ALUOp = 00 3 New state would look like…
![27 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address : lw++ $6,8($7) Memory addresscontent lw++ encoding … … Part 2: NEW.](http://images.slideplayer.com./26/8652725/slides/slide_27.jpg "To make this work, need to assert other control signals in State 3 to do an add operation: ALUSrcA = 1 # select A input ALUSrcB = 01# select 4 input ALUOp = 00# perform add MemRead IorD = 1 ALUSrcA = 1 ALUSrcB = 01 ALUOp = 00 3 New state would look like….")
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28 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address 1000 10 : lw++ $6,8($7) Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 Part 2: NEW! 1 10000 10 See control logic discussion do add 01 10004 10 ALUOut contains 10004 10
![28 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 4, State 3: Get data from memory MDR Memory[ALUOut] || ALUOut [A] + 4 address : lw++ $6,8($7) Memory addresscontent lw++ encoding … … Part 2: NEW.](http://images.slideplayer.com./26/8652725/slides/slide_28.jpg "See control logic discussion do add ALUOut contains")
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Now, to finish, we need to support the write back of both the MDR register AND the ALUOut register For dramatic effect, let’s continue on another slide… 29
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Option A: Write back MDR and ALUOut in the same CC… 30
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31 Register file addresscontent 6 (00110)9 10 7 (00111)10000 10 PC value: 1004 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 5, State 12: Write data back… RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut address 1000 10 : lw++ $6,8($7) Memory addresscontent 1000 10 lw++ encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 Option A Aw, snap! With existing datapath, only 1 register can be written at a time…
![31 Register file addresscontent 6 (00110) (00111) PC value: OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 5, State 12: Write data back… RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut address : lw++ $6,8($7) Memory addresscontent lw++ encoding … … Option A Aw, snap.](http://images.slideplayer.com./26/8652725/slides/slide_31.jpg "With existing datapath, only 1 register can be written at a time….")
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Option A: Write back MDR and ALUOut in the same CC… 32 Solution: Add register file hardware Update the FSM Let’s update the register file hardware 1 st …
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33 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 5, State 12: Write data back… RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut address 1000 10 : lw++ $6,8($7) Option A Can keep existing hardware the same, but need to add: Another address port “Write register 2” Another data port “Write data 2” Another control signal RegWrite2 IR(25:21) – i.e. 00111 2 Input to Write Register 2 ALUOut (10004 10 ) Input to Write Data 2 New control signal: RegWrite2
![33 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 5, State 12: Write data back… RF[IR(20-16)] MDR || RF[IR(25:21)] ALUOut address : lw++ $6,8($7) Option A Can keep existing hardware the same, but need to add: Another address port Write register 2 Another data port Write data 2 Another control signal RegWrite2 IR(25:21) – i.e.](http://images.slideplayer.com./26/8652725/slides/slide_33.jpg "Input to Write Register 2 ALUOut ( ) Input to Write Data 2 New control signal: RegWrite2.")
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New FSM diagram is thus: 34 RegDst = 0 RegWrite MemtoReg = 1 RegWrite2 12 lw++ Need a new state because we want to do different things for lw and lw ++
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Option B: Write back MDR and ALUOut in the different CCs… 35
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36 Register file addresscontent 6 (00110)9 10 70 10 7 (00111)10000 10 PC value: 1004 10 Memory addresscontent 1000 10 lw encoding … … 10000 10 50 10 10004 10 60 10 10008 10 70 10 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR 0 1 6 10 70 10 address 1000 10 : lw++ $6,8($7) Same as normal lw
![36 Register file addresscontent 6 (00110)9 10 (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR address : lw++ $6,8($7) Same as normal lw](http://images.slideplayer.com./26/8652725/slides/slide_36.jpg "36 Register file addresscontent 6 (00110)9 10 (00111) PC value: Memory addresscontent lw encoding … … OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 5, State 4: Write data from memory to the register file RF[IR(20:16)] MDR address : lw++ $6,8($7) Same as normal lw")
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37 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits 15-0 10001100111001100000 0000 0000 1000 Cycle 5, State 13: Write data from ALUOut to the register file RF[IR(25:21)] ALUOut address 1000 10 : lw++ $6,8($7) Aw, snap! No path for bits 25:21 of IR to use as write address… To fix: Add another input to mux Now need 2 control signals instead of 1 00 01 10 IR(20:16) IR(15:11) IR(25:21)
![37 OpcodeSourceDestinationImmediate value Bits 31-26Bits 25-21Bits 20-16Bits Cycle 5, State 13: Write data from ALUOut to the register file RF[IR(25:21)] ALUOut address : lw++ $6,8($7) Aw, snap.](http://images.slideplayer.com./26/8652725/slides/slide_37.jpg "No path for bits 25:21 of IR to use as write address… To fix: Add another input to mux Now need 2 control signals instead of IR(20:16) IR(15:11) IR(25:21).")
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New FSM diagram is thus: 38 RegDst = 10 RegWrite MemtoReg = 0 13 lw++ Notes: RegDst = 10 Selects IR(25:21) RegWrite Enables register file to be written MemtoReg = 0 Selects ALUOut as input to the register file
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