1. Chap. 4 Modules and Ports

2. 2 Modules and Ports Modules Ports Hierarchical Names Summary

3. 3 Modules Basic component in Verilog for describing/defining a hardware module ( ); … … endmodule

4. 4 Components of Modules - I Variables Declaration Dataflow Statement Module Instantiation Behavior Statement Tasks and Functions

5. 5 Components of Modules - II These components are optional!

6. 6 An Example – SR Gate

7. 7 Module Description of SR Gate No “variable declaration”, “dataflow statement” and “behavioral statement” are included in this module

8. 8 Testbench for SR Gate

9. 9 Modules and Ports Modules Ports Hierarchical Names Summary

10. 10 Ports I/O Interface used to communicate with external module “No” port declaration if do not need to communicate with other module, such as Top module

11. 11 Module fulladd4 has five ports while top has no port. a, b, and c_in are input ports and sum and c_out are output ports. List of Ports - I

12. 12 List of Ports - II

13. 13 Port Declaration Three types  input  output  inout

14. 14 Port Declaration of fulladd4 Default data type of I/O ports is regarded as “wire”.

15. 15 Port Declaration of D Flip-Flop

16. 16 ANSI C Port Declaration

17. 17 Input Port  Internal view － viewed as “a wire/net”  External view － can be connected to a reg or wire Output Port  Internal view － declared as a reg or wire  External view － only be connected to a wire Inout Port  viewed as a wire/net regardless of internal or external module Port Connection Rules - I

18. 18 Port Connection Rules - II

19. 19 Mismatch of internal and external port connections  Simulation should issue a warning for this condition Floating of port connection  Fulladd4 fa0(sum,, a, b, c_in); // c_out floating Illegal connection of internal and external ports Port Connection Rules - II

20. 20 An Example of Illegal Internal/External Port Connection

21. 21 Connecting Ports to External Signals Connecting ports by module declaration sequence Connecting ports by name

22. 22 Connecting Ports by Module Declaration Sequence

23. 23 Connecting Ports by Name Fulladd4 fa_byname(.c_out(c_out),.sum(sum),.b(b),.c_in(c_in),.a(a)); Fulladd4 fa_byname(.sum(sum),.b(b),.c_in(c_in),.a(a));

24. 24 Modules and Ports Modules Ports Hierarchical Names Summary

25. 25 Hierarchical Names Named each instance, variables and signals in hierarchical design Root module  Never be referenced by other modules, such as stimulus Hierarchical instances are separated by dot sign “.” $display (“%m”)  display hierarchical level of that module

26. 26 An Example of Hierarchical Names

27. 27 Modules and Ports Modules Ports Hierarchical Names Summary

28. 28 Summary A module contains  module, endmodule keyword  Port list, port declaration, variable declaration, dataflow statement, behavioral block, module instantiation, task and function Ports provide an interface communicated with external environment  Input, output, inout Connecting ports to external signals  By port declaration sequence  By port name Hierarchical name  Root module  Separated by “.” between instances