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Published byDominic Nicholson Modified over 8 years ago
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Application to the automatic extraction of circuit shapes Charles Hymans Modular analysis of a circuit description language by Abstract Interpretation
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6 April 2002Designing Correct Circuits2 lfp F (lfp G) Concrete semantics fix-point of F Galois connection ( , ) links concrete D and abstract A domain Sound abstract semantics fix-point of G algorithm A. I. design flow F G D A D A
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6 April 2002Designing Correct Circuits3 Shape analysis for RTL VHDL A <= B or C; A B C orA B C
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6 April 2002Designing Correct Circuits4 Generic modules? entity example generic(n : integer) port(A : bit_vector(1 to n), B : bit_vector(1 to 2*n)) for I in 1 to n A[I] <= not B[I + 1]; end; No a-priori bound on n !
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6 April 2002Designing Correct Circuits5 Modular analysis Semantics of a module? Representation for infinite shapes? A B 1...n n + 1 infinite !
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6 April 2002Designing Correct Circuits6 Operational semantics Execution builds a circuit State : (l, E, G, S) VHDL command basic operators 7 basic operators modify (E, G) assert, create_int, connect...
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6 April 2002Designing Correct Circuits7 Trace semantics? Chopped semantics! M N call return M N
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6 April 2002Designing Correct Circuits8 Fix-point for chopped semantics F(X)(g) = entry(g) {s 0 … s n+1 | s 0 … s n X(g), s n s n+1 } {s 0 … s n+1 | s 0 … s n X(g), s n call(f), s n t 0, t 0 … t m X(f), t m return, t m s n+1 }
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6 April 2002Designing Correct Circuits9 Abstract domain At each program point l Possible values of integer variables numerical domain Shapes built since module entry decorated connection graph
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6 April 2002Designing Correct Circuits10 Numerical domains Intervals affine subspaces octagons polyhedra X [a X, b X ] Y [a Y, b Y ] aX + bY = c X Y c aX + bY c Symbolic representation for numerical functions
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6 April 2002Designing Correct Circuits11 Decorated connection graph finite ! l + 1 = r A B 1...n n+1 infinite ! A B for I in 1 to n A[I] <= not B[I + 1]; end;
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6 April 2002Designing Correct Circuits12 Abstract operators Operational semantics expressed thanks to 7 basic operators Design only abstract operators abstract module plug-in sound operators sound analysis
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6 April 2002Designing Correct Circuits13 Example: wire connection A[2*I + 1] <= not B[J]; left expression: l = 2*I + 1 environment: I = J right expression: r = J resulting constraint: l = 2 * r + 1
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6 April 2002Designing Correct Circuits14 Wire connection (cont.) IJ lr resulting connection environment leftright
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6 April 2002Designing Correct Circuits15 Conclusion Modular analysis Decorated connection graph Quickly applicable to other languages Data-dependency: all VHDL Timed dependencies: “ B depends on A with a delay of 3 cycles”
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