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9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU1 Shift Registers.

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Presentation on theme: "9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU1 Shift Registers."— Presentation transcript:

1 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU1 Shift Registers

2 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU2 Class 25 – Shift Registers  Multiplication by 2 (division by 2)  Shift Register topology  Material from section 7-6 of text

3 Effect of a shift operation  A single shift is multiplication by 2  Consider the operation 6 x 2 = 12 0110 x 0010 0000 0110. Will skip last 2 rows of terms of 0s 01100  Note that this result is just a shift by 1 position. 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU3

4 Multiplication by shift  Reference base 10. To multiply or divide by 10 you just move the decimal point, or in scientific notation, adjust the exponent.  In base 2 you can move the binary point Right by 1 position to multiply by 2 Left by 1 position to divide by 2  Or shift the binary number on a fixed binary point Left by 1 position to multiply by 2  1110. x 2  11100. Right by 1 position to divide by 2  11100.  2  1110. 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU4

5 A 4-bit shift register  Shift word one bit each clock.  Sometimes called a FIFO or First in First Out across all the bits of the word. 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU5

6 SR with Parallel Load  Shift Register with Parallel Load 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU6

7 Bidirectional Shift Register  Also have load operation  Representation is only partial  Note the serial input and output 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU7

8 Operations allowed  Several operations supported 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU8

9 The mux in from of each F/F  The multiplexer in front of each flip flop routes the selected input to the FF input. The current FF output The less significant FF output (or serial in-lsb) The most significant FF output (or serial out-msb) A new input to load. 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU9

10 The look  The register setup  Note that all signal routing is not shown. 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU10

11 Class 25 assignment  Covered part of section 7-6  Problems for hand in Nothing new  Problems for practice Nothing new  Reading for next class: counters from 7-6 9/15/09 - L26 Shift RegistersCopyright 2009 - Joanne DeGroat, ECE, OSU11

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