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ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 2 Part 7 Tom Kaminski & Charles.

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Presentation on theme: "ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 2 Part 7 Tom Kaminski & Charles."— Presentation transcript:

1 ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 2 Part 7 Tom Kaminski & Charles R. Kime

2 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 2 NAND and NOR Implementation

3 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 3 NAND Gates

4 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 4 NAND Gates (Cont.)

5 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 5 NAND Implementation

6 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 6 NAND Implementation (Cont.)

7 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 7 Degenerate AND Term

8 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 8 NAND-NAND Example

9 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 9 NAND-NAND Example

10 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 10 NOR Gates

11 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 11 NOR Implementation

12 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 12 Useful Transformations

13 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 13 Graphical Transformations

14 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 14 General Two-level Implementations

15 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 15 General Implementations (Cont.)

16 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 16 Implementation Example

17 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 17 Implement F in AND-NOR form Implement the network:

18 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 18 Multi-level NAND Implementations Add inverters in two-level implementation into the cost picture Attempt to “combine” inverters to reduce the term count Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS

19 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 19 Multi-level NAND Example 1 F = A B’ + A C’ + B A’ + B C’ = A A’ + A B’ + A C’ + B A’ + B B’ + B C’ = A (A’ + B’ + C’) + B (A’ + B’ + C’) F A C B 7 inputs and 4 gates 15 inputs and 8 gates* * Counting inverters (NOTS) as 1 input and 1 gate

20 ECE/CS 352 Digital System Fundamentals Chapter 2 Page 20 Multilevel NAND Example 2 F = AB + AD’ + BC + CD’ 12 inputs & 5 gates = A(B + D’) + C(B + D’) 8 inputs & 5 gates F A C B D

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