1. 1 K-Maps, Multi-level Circuits, Time Response Today: Reminder: Test #1, Thu 7-9pm K-map example, espressoFirst Hour: K-map example, espresso –Section 2.3 of Katz’s Textbook –In-class Activity #1 Second Hour: Multi-Level Logic, All- NAND/NOR Circuits, Time Response Section 3.1 of Katz’s Textbook –In-class Activity #2

2. 2 Recap: K-maps A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables A donut-like representation ! 1 1 1

3. 3 Recap: K-maps A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables 1 1 1 The “Boolean Lasso” expresses the uniting theorem Remember: diagonally-adjacent terms cannot be united

4. 4 Recap: K-maps A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables 1 1 1 The bigger the lasso, the smaller the result

5. 5 K-map Method Summary Step 1 — Group 1s starting with the largest cube, then next largest, etc. Step 2 — If 1 is covered by only one cube, that cube is an essential covering Step 3 — Use largest covering for 1s not covered by essential coverings Step 4 — Include singletons Step 5 — Translate to Boolean formStep 5 — Translate to Boolean form

6. 6 Example A circuit that compares two 2-bit numbers Comparator AB CD AB < CD AB = CD AB > CD 4 input bits 3 output bits

7. 7 Truth Table A B C D = 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 AB is one two-bit number and CD is the other AB is held constant and compared with the 4 possible values of CD Notice the three outcomes ( = ) are mutually exclusive 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0

8. 8 Fill in the K-maps AB CD 00011110 00 1000 01 0100 11 0010 10 0001 AB CD 00011110 00 0000 01 1000 11 1101 10 1100 AB CD 00011110 00 0111 01 0011 11 0000 10 0010 = <>

9. 9 The “=“ Function:SOP AB CD 00011110 00 1000 01 0100 11 0010 10 0001 = No simpler SOP form! Makes sense: XOR-gates! No simpler SOP form! Makes sense: XOR-gates! “=“ “=“ = A’B’C’D’ + A’BC’D + ABCD + AB’CD’

10. 10 The “=“ Function: POS AB CD = “=“ “=“ = (A C' + A' C + B D' + B' D)' = (A' + C)(A + C')(B' + D)(B + D')

11. 11 The “<“ Function: SOP AB CD 00011110 00 0000 01 1000 11 1101 10 1100 < “<“ “<“ = A’C + B’ C D + A' B‘D

12. 12 The “<“ Function: POS AB CD < “<“ “<“ = (A C' + B C' + C' D' + A B +A D')' = (A' + C)(B' + C)(C + D)(A' + B')(A' + D)

13. 13 The “>” Function: SOP AB CD “>“ “>“ = AC’ + ABD’ + BC' D' >

14. 14 The “>” Function: POS AB CD > “>” “>” = (A' C + A' D + C D + A' B' +B' C)' = (A + C')(A + D')(C' + D')(A + B)(B + C')

15. 15 Simplifying Larger Functions Use Logic Minimization software. Example: espresso –Public domain software –Easy to use, but not a toy! –Used for real designs. Often the cost of a circuit depends on the number of –The number of terms –Number of literals. espressofewer different termsespresso tries to achieve fewer different terms.

16. 16 espresso Example a 2 a 1 a 0 b 2 b 1 b 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 x x x 1 1 0 x x x 1 1 1 x x x Minimize the following 3-input, 3-output function: 3 easy Steps: 1.Translate the given function into the espresso file format. 2.Run espresso 3.The espresso output file has the simplified function!

17. 17 Input to espresso.i 3.o 3.p 8 000 001 001 010 010 011 011 100 100 000 101 --- 110 --- 111 ---.e - # input variables - # output variables - # table rows (optional) - inputs, outputs,... - dash denotes don’t care - marks the end (optional) a 2 a 1 a 0 b 2 b 1 b 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 x x x 1 1 0 x x x 1 1 1 x x x

18. 18 Output espresso Output.i 3.o 3.p 4 0-0 001 -11 100 -01 010 -10 010.e This looks familiar but is new. Output Boolean expressionsOutput Boolean expressions –For each column, look for the rows that are 1, the AND terms –Then OR the AND terms –e.g., AND term 0-0 is a 2 a 0 b 2 = a 1 a 0 b 1 = a 1 ' a 0 + a 1 a 0 ' b 0 = a 2 ' a 0 ' b 2 = a 1 a 0 b 1 = a 1 ' a 0 + a 1 a 0 ' b 0 = a 2 ' a 0 ' These dashes denote absent variables

19. 19 Comparison mintermminterm expression b 2 = a 2 ' a 1 a 0 b 1 = a 2 ' a 1 ' a 0 + a 2 ' a 1 a 0 ' b 0 = a 2 ' a 1 ' a 0 ' + a 2 ' a 1 a 0 ' b 2 = a 2 ' a 1 a 0 b 1 = a 2 ' a 1 ' a 0 + a 2 ' a 1 a 0 ' b 0 = a 2 ' a 1 ' a 0 ' + a 2 ' a 1 a 0 ' espressoespresso expression b 2 = a 1 a 0 b 1 = a 1 ' a 0 + a 1 a 0 ' b 0 = a 2 ' a 0 ' b 2 = a 1 a 0 b 1 = a 1 ' a 0 + a 1 a 0 ' b 0 = a 2 ' a 0 ' 4 different terms, used 4 times. 8 literals. 1 2-input OR and 4 2-input ANDs Simpler 4 different terms, used 5 times. 12 literals. 2 2-input ORs; 4 3-input ANDs We’ll learn to use espresso during the next studio!

20. 20 Do Activity #1 Now Reference: –Section 2.3 of Katz’s Textbook –More K-maps –Translating to/from espresso format

21. 21 Multilevel Logic Boolean networks can have space-time tradeoffs. Smaller  slower. Bigger  faster. multilevelIf you factor out common expressions, you may get a form with fewer gates, but with more than 2 levels of gates  multilevel Boolean networks can have space-time tradeoffs. Smaller  slower. Bigger  faster. multilevelIf you factor out common expressions, you may get a form with fewer gates, but with more than 2 levels of gates  multilevel

22. 22 Multilevel Circuits Reduced sum of products form: X = A D F + A E F + B D F + B E F + C D F + C E F + G 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) 1 2 3 4 5 6 7 A A B B C C D D D E E E F F F F F F G x 1 23 4 A B C D E F G x Factored form: X = (A + B + C) (D + E) F + G 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)

23. 23 NAND-NAND networks SOP expressions have ANDs and ORs. You can convert it to use all NANDs (or all NORs). Necessary facts: –DeMorgan's theorem active low –Many logic chips have outputs that are active low bubble –Active low outputs are indicated by the presence of a bubble

24. 24 Conversion of Forms NORNAND DeMorgan's Law: (A + B)' = A' B'; (A B)' = A' + B' NOR is the same as AND with complemented inputs NAND is the same as OR with complemented inputs ORAND Written differently: A + B = (A' B')'; (A B) = (A' + B')' OR is the same as NAND with complemented inputs AND is the same as NOR with complemented inputs

25. 25 Equivalent Forms AA BB º OR AA B B º Nand NAND AA BB º AND AA B B º NOR

26. 26 Conversion Between Forms bubblesIt is possible to convert from networks with ANDs and ORs to networks with NANDs and NORs by introducing the appropriate inversions (bubbles) bubblesTo preserve logic levels, bubbles must be introduced in pairs

27. 27 (1) A B C D (3) A B C D NAND A B C D AND OR (2) A B C D NAND (4) AND/OR to NAND/NAND

28. 28 AND/OR to NAND/NAND bubble-pushingUsed bubble-pushing to simultaneously add or remove 2 bubbles to an output and associated input. Can also just use Boolean algebra: Can also convert to NOR/NOR form. f = A B + C D(AND-OR) = ( (A B)' (C D)' )'(NAND-NAND) revisited

29. 29 Time Response Terms Terms: gate delay gate delay — time for change at input to cause a change at output - minimum delay vs. typical/nominal delay vs. maximum delay. - careful designers design for the worst case! propagation delay propagation delay — same as gate delay rise time rise time — time for output to transition from low to high voltage fall time fall time — time for output to transition from high to low voltage

30. 30 Time Response in Combinational Networks emphasis on timing behavior of circuits waveforms used to visualize what is happening use simulation to create these waveforms hazardsmomentary changes of signals at the outputs: hazards –can be useful — pulse shaping circuits glitches: –can be a problem — glitches: incorrect circuit operation

31. 31 Time Response Example Pulse Shaping Circuit What is the value of F if A = 0? What is the value of F if A = 1? 3 gate delays D remains high for three gate delays after A changes from low to high F is not always 0! What happens when A changes from 0 to 1 and back again?

32. 32 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook Required Reading: – Sec 4.1 of Katz This reading is necessary for getting points in the Studio Activity!