1. 1 Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits Nishant Patil Jie Deng H.-S. Philip Wong Subhasish Mitra Departments of Electrical Engineering & Computer Science Stanford University

2. 2 Misaligned Carbon Nanotubes (CNTs) Misaligned-CNT-Immune Logic Design Aligned CNTs on Quartz – Prof. Zhou, USC

3. 3 CNFET Transistor Layout Substrate (e.g Quartz) CNT undoped region Lithographic Gate CNT doped region Side ViewTop View Oxide CNT undoped region

4. 4 Perfect CNFET Inverter Layout V. Derycke et al., Nano Letters, p. 453, 2001. N+ doped Semiconducting CNTs Vdd Contact Output Contact Gnd Contact Gate Input P+ doped Semiconducting CNTs 64nm = 4λ 4nm

5. 5 CNFET Fabrication Process  Define cell regions on substrate  Etch CNTs outside cell regions  Define gates and contacts  Chemically dope CNTs Vdd Gnd Out1 Out2 Gate A Gate B Gate A Gate B Gate A Gate B Out1 Out2 P+ doped CNTs N+ doped CNTs Vdd Gnd Undoped (intrinsic) CNTs

6. 6 CNFET Imperfections: Misaligned CNTs Out Gate A Gate B Gate A Gate B Vdd A A B Short Vdd Gnd Out B A B C D Wanted: AC + BD Got: AC + BD + AD Gnd Vdd Wanted: A+B in pullup; Got: Short

7. 7 B A A B Misaligned-CNT-Immune NAND Design Vdd Gnd Out 1.Grow CNTs 2.Define gates and contacts 3.Chemically dope P-type region 4.Chemically dope N-type region 5.Etch Undoped region enables misaligned- CNT-immune design

8. 8 B A A B Misaligned-CNT-Immune NAND Design Vdd Gnd Out 1.Grow CNTs 2.Define gates and contacts 3.Etch CNTs 4.Chemically dope P-type region 5.Chemically dope N-type region Etched region enables misaligned- CNT-immune design

9. 9 Generalized Algorithm Characterize Layout  Misaligned-CNT-Immune OR  Misaligned-CNT-Vulnerable Implement Arbitrary Logic function  Misaligned-CNT-Immune Layout

10. 10 Contact Doped Gate A Gate B Contact CCC GA GB DDD D DDD D DDD Misaligned-CNT-Vulnerable NAND: Pull-up A B Implemented Function A or B or (A AND B) or 1 == 1 != A or B A B Contact 1 1 A B 1 CCC Path 1: C-D-A-D-C : fn = A Path 2: C-D-B-D-C : fn = B Path 3: C-D-A-D-B-D-C : fn = A & B Path 4: C-D-C : fn = 1 Intended Function A or B

11. 11 Misaligned-CNT-Immune NAND: Pull-up UD GAGB Doped Gate B Contact Doped Contact Gate A Doped Undoped Intended Function A or B Implemented Function A or B or (A and B) or (A and B and 0) == A or B B Contact A Path 1: C-D-A-D-C : fn = A Path 2: C-D-B-D-C : fn = B Path 3: C-D-A-D-B-C : fn = A & B Path 4: C-D- B- UD- A- D-C : fn = 0 … 1 1 A B 1 1 0 Contact

12. 12 Misaligned-CNT-Immune Arbitrary Function Gates A + (B + C)(D + E) Undoped regions CNTs CB Vdd/ Gnd Contact A Output Contact E D Intermediate Contact Immune to ANY number of misaligned CNTs Arbitrary logic function Formal correctness proof (Details in paper)

13. 13 Simulation Results Penalties over Vulnerable CNFET Circuit Cell TypeAreaEnergyDelay [max {rise, fall}] nand2 -1%3%-7% nand3 11%15%10% nor2 -1%5%1% nor3 11%16%10% aoi21 -2%1% Full Adder 12%10%7% Misaligned-CNT-Immune vs. Misaligned-CNT-Vulnerable CNFET model  Deng & Wong, SISPAD 06  10% accuracy: DC & AC measurements  Amlani, et al., IEDM 06 Significantly less penalty vs. traditional fault tolerance

14. 14 Conclusion Misaligned CNT Immune Design  Perfect alignment not needed: immune by design  Ideal case: 13X better EDP vs. 32nm CMOS  Efficient misaligned-CNT-immune circuits  Significantly less overhead than replication Metallic CNTs

15. 15 Thank You

16. 16 Misaligned-CNT-Vulnerable NAND: Pulldown A B Gate B Contact Gate A Doped Intended Function A and B Path: C-D-A-D-B-D-C Implemented Function A and B Contact Doped Gate A Gate B Contact Doped A B Contact 1 1 A 1 B 1 1