1. Lecture 09 NAND and XOR Implementations

2. Overview °Developing NAND circuits °Two-level implementations Convert from AND/OR to NAND (again!) °Multi-level NAND implementations Convert from a network of AND/ORs °Exclusive OR Comparison with SOP °Parity checking and detecting circuitry Efficient with XOR gates!

3. Gates A X X = (A + B)’ B AND A X = A B X or B X = AB 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR A X X = A + B B I A X X = A’ 0 1 1 0 Buffer A X X = A A X 0 1 NAND A X X = (AB)’ B 0 0 1 0 1 1 1 0 1 1 1 0 NOR 0 0 1 0 1 0 1 0 0 1 1 0 XOR Exclusive OR A X = A  B X or B X = A’B + AB’ 0 0 0 0 1 1 1 0 1 1 1 0 A X = (A  B)’ X or B X = A’B’+ AB 0 0 1 0 1 0 1 0 0 1 1 1 XNOR Exclusive NOR or Equivalence A B X A X A B X

4. Axioms and Graphical representation of DeMorgan's Law Commutative Law Associative Law Distributive Law Consensus Theorem

5. nand nor and or not Recall that symbolic DeMorgan’s duals exist for all gate primitives The above alternate symbols can be used to facilitate the analysis and design of NAND and NOR gate networks. Network Conversion Using Alternate Gate Symbols

6. NAND-NAND & NOR-NOR Networks DeMorgan’s Law: (a + b)’ = a’ b’ (a b)’ = a’ + b’ a + b = (a’ b’)’ (a b) = (a’ + b’)’ push bubbles or introduce in pairs or remove pairs.

7. NAND-NAND & NOR-NOR Networks

8. NAND-NAND Networks °Mapping from AND/OR to NAND/NAND

9. NAND-NAND Networks

10. Implementations of Two-level Logic °Sum-of-products AND gates to form product terms (minterms) OR gate to form sum °Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product

11. Two-level Logic using NAND Gates °Replace minterm AND gates with NAND gates °Place compensating inversion at inputs of OR gate

12. Two-level Logic using NAND Gates (cont’d) °OR gate with inverted inputs is a NAND gate de Morgan's:A' + B' = (A B)' °Two-level NAND-NAND network Inverted inputs are not counted In a typical circuit, inversion is done once and signal distributed

13. Two-level Logic using NAND Gates (cont’d)

14. Conversion Between Forms °Convert from networks of ANDs and ORs to networks of NANDs and NORs Introduce appropriate inversions ("bubbles") °Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions Do not alter logic function °Example: AND/OR to NAND/NAND A B C D Z A B C D Z NAND

15. Z = [ (A B)' (C D)' ]' = [ (A' + B') (C' + D') ]' = [ (A' + B')' + (C' + D')' ] = (A B) + (C D) Conversion Between Forms (cont’d) °Example: verify equivalence of two forms A B C D Z A B C D Z NAND

16. Conversion to NAND Gates °Start with SOP (Sum of Products) circle 1s in K-maps °Find network of OR and AND gates

17. ABCDEFGABCDEFG X Multi-level Logic °x = A D F + A E F + B D F + B E F + C D F + C E F + G Reduced sum-of-products form – already simplified 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) °x = (A + B + C) (D + E) F + G Factored form – not written as two-level S-o-P 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)

18. Level 1Level 2Level 3Level 4 original AND-OR network A C D B B C’C’ F introduction and conservation of bubbles A C D B B C’C’ F redrawn in terms of conventional NAND gates A C D B’B’ B C’C’ F Conversion of Multi-level Logic to NAND Gates °F = A (B + C D) + B C'

19. A X B C D F (a) Original circuit A X B C D F (b) Add double bubbles at inputs D’D’ A X’X’ B C F (c) Distribute bubbles some mismatches D’D’ A X B C F X’X’ (d) Insert inverters to fix mismatches Conversion Between Forms °Example

20. Making NAND circuits (Ex) °The easiest way to make a NAND circuit is to start with a regular, primitive gate-based diagram. °Two-level circuits are trivial to convert, so here is a slightly more complex random example.

21. Converting to a NAND °Step 1: Convert all AND gates to NAND gates and convert all OR gates to NAND gates. AND OR

22. Converting to NAND °Step 2: Cancel all pairs of inverters ((x’)’ = x)..

23. Exclusive-OR and Exclusive-NOR Circuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels.

24. Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level. Exclusive-NOR Circuits

25. XNOR gate may be used to simplify circuit implementation. Exclusive-NOR Circuits

26. XOR Function °XOR function can also be implemented with AND/OR gates (also NANDs).

27. FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system. Parity Generation and Checking

28. Summary °Follow rules to convert between AND/OR representation and symbols °Conversions are based on DeMorgan’s Law °NOR gate implementations are also possible °XORs provide straightforward implementation for some functions °Used for parity generation and checking XOR circuits could also be implemented using AND/Ors °Next time: Hazards