1. Mohammed Shahid Ali, A.R Nazmus Sakib, Dereje Agonafer. The University of Texas at Arlington.

2.  Trend in 3D packaging  3D TSV Package Introduction and challenges.  Issues addressed in this paper. Modeling descriptions, methodology and properties.Modeling descriptions, methodology and properties. Crack formulation methodology in ANSYS and cut boundary application to model.Crack formulation methodology in ANSYS and cut boundary application to model. Variation of die and substrate thickness and its effects.Variation of die and substrate thickness and its effects.  Validation and Results.  Conclusion.

3.  Electronic products becoming revolutionized.  Miniaturization and improved performance a hot topic.

4.  3D TSV technology advantages:  Increased performance.  Reduced form factor.  Cost reduction.  High-bandwidth interconnection between stacked chips.

5.  3D TSV technology still faces some issues.  CTE mismatch issues and its effects.  Critical areas in TSV package.

6.  Motivation for this work.  Crack propagation in 3D TSV package & calculation of SIF in silicon die.  Methodology used (FEM, submodeling technique).  Variation of die and substrate thickness.

7.  A 2 die 3D flip chip package with TSV.  Modeled using linear elastic properties.  Modeling Technique (diameter and dielectric, CRE).  Simulation steps.  Symmetry boundary conditions and constraints.

8. Figure 1. Global Model with Exploded Submodel 1 Submodel 1

9.  Crack shape options in current ANSYS bundle. bundle.  Crack modeling on interior and exterior surfaces of the model. Which one’s possible?  Symmetrical slicing of the model and subsequent boundary conditions applied.  Crack positioning, Locations & Data calculated.

10. Figure 2. Crack formulation in the Silicon die at the mid-section of Submodel 2.

11. Figure. SIF (K 2 ) distribution at crack location in Submodel 2.

12. Figure. K 1 /Crack Location plot.

13. Figure. K 2 /Crack location plot.

14. Figure. K 3 /Crack location plot.

15.  Analysis on crack driving force. Figure. J-Integral vs Substrate Thickness Plot

16. Figure. J-Integral vs Die Thickness Plot.

17. Analysis on stress distribution in solders.Analysis on stress distribution in solders. Any significant results in solders with respect to die and substrate variation?Any significant results in solders with respect to die and substrate variation?

18.  Successfully modeled crack in the interior of TSV/Silicon interface with subsequent submodels and cut boundary constraints.  Critical areas where K 1, K 2, K 3 are prominent are highlighted.  SIF values compared with fracture toughness of silicon.  Effects on solder joints studied.