1. Lecture 11, Advance Digital Design
Hassan Bhatti, Spring 2009

2. Today’s Topics Simple Adder Architectures Efficient Adders
Division Algorithms
Multipliers
Efficient Multipliers (Booth Multiplier, Wallace Tree)

3. HALF ADDER

4. HALF Adder in Verilog

5. Half Adder Using Data Flow

6. Full Adder Architecture

7. FULL adder using Data Flow Model

8. Ripple Carry Adder

9. Ripple Carry Adder

10. Pipeline Adders: Single Stage

11. Single Stage Pipelining

12. Three Stage Pipeline Adder

13. Carry Select Adder

14. Uniform Stage Carry Select Adder

15. Non Uniform Stage Carry Select Adder

16. Non Uniform Stage Carry Select Adder

17. Non Uniform Stage Carry Select Adder

18. Carry Look Ahead Adder

19. Carry Look Ahead

20. Carry Look Ahead

21. Carry Look Ahead Adders

22. Carry Look Ahead Block

23. Delay of Carry Look Ahead

24. Delay of Carry Look Ahead

25. Implementation of Carry Look Ahead

26. Area and Delay of Adders

27. Conditional Sum Adder

28. Conditional Sum Adder

29. Conditional Sum Adder: Example

30. Conditional Sum Adder: Example 8-Bits

31. Conditional Sum Adder: Example 16-Bits

32. Dividers-1:
For Details See Chapter Bernard Sklar, Digital Communication

33. Dividers-1: Verification of the Result
For Details See Chapter Bernard Sklar, Digital Communication

34. Dividers-2
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design

35. Dividers-2: Example
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design

36. Divisors-2: Easy Circuit
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design

37. Divisors-2: Improved Circuit
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design

38. Courtesy and Acknowledgement of Slides and Pictures
Adder Architecture are Taken for Dr. Shoab A. Khan Lectures