1. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

2. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 2 A Generic Digital Processor

3. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 3 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

4. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 4 Arithmetic building blocks  Speed and power of arithmetic components often dominates the overall system performance  For each module, multiple topologies and ways of design exists, with each of them has its own advantages  A global picture is of crucial importance. A designer focus their attention on gates or transistors that have the largest impact on their goal function. Non-critical components can be developed routinely.  Typically two optimization process: logic optimization (re-arrange Boolean equations so that a faster or small circuit could be obtained) and circuit optimization (manipulate circuit topology and transistor sizes to optimize speed)

5. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 5 Bit-Sliced Design Since the same operation has to be performed on each bit of a data word, the data path can consist of the number of bit slices (equal to the word length), each operating on a single bit – hence the term bit-sliced

6. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 6 Adders

7. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 7 Full-Adder

8. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 8 The Binary Adder

9. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 9 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

10. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 10 Complimentary Static CMOS Full Adder 28 Transistors

11. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 11 Complimentary Static CMOS Full Adder  Large PMOS stacks are present in both carry and sum generation circuits  Intrinsic load capacitance of C o signal is large and consists of eight capacitance components  There is one more inverter delay for carry and sum (worse when the load capacitance is large)  Note that critical signal C i closer to the output node

12. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 12 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete (D) = A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for

13. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 13 Transmission Gate XOR When B=1, M1/M2 inverter, M3/M4 off, so F=AB When B=0, M1/M2 off, M3/M4 transmission gate, so F=AB

14. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 14 Transmission Gate Full Adder

15. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 15 Manchester Carry Chain Generate (G) = AB Propagate (P) = A  B Delete =A B Prevent floating C o

16. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 16 Full-Adder

17. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 17 Manchester Carry Chain

18. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 18 Manchester Carry Chain Stick Diagram

19. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 19 Manchester Carry Chain  Delay for the Manchester Carry Chain can be modeled similar to a linearized RC network as in transmission-gates  This means the propagation delay is quadratic in the number of bits N (but does not imply the delay will be larger than the ripple carry adder)  It might be necessary to insert signal buffering inverters.  Still a ripple carry adder, typically only good for small word length (<8/16 bits)  We need faster adders for computer and multimedia applications with word length 32-128 bits

20. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 20 Carry-Bypass Adder Also called Carry-Skip Break the bit-slice organization G0G0 G0G0 P1P1 P1P1 “delete” or “generate”

21. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 21 Carry-Bypass Adder (cont.) t adder = t setup + Mt carry + (N/M-1)t bypass + (M-1)t carry + t sum T setup : overhead time to create G, P, D signals (worst case)

22. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 22 Carry Ripple versus Carry Bypass (both still linear)

23. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 23 Carry-Select Adder

24. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 24 Carry Select Adder: Critical Path

25. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 25 Linear Carry Select t adder = t setup + Mt carry + (N/M)t mux + t sum

26. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 26 Square Root Carry Select M

27. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 27 Adder Delays - Comparison Bypass

28. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 28 LookAhead - Basic Idea

29. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 29 Look-Ahead: Topology Expanding Lookahead equations: All the way:

30. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 30 Look-Ahead Adder: Logarithmic adder

31. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 31 Carry Look-Ahead Trees Can continue building the tree hierarchically. =G 1:0 +P 1:0 C 0 (G 1:0 =G 1 +P 1 G 0 P 1:0 =P 1 P 0 ) C 0 = G 0 + P 0 C in C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 C 1 C 3 = G 3 + P 3 C 2 C 0 = G 0 + P 0 C in C 1 = G 1 + P 1 C 0 = G 1 + G 0 P 1 + P 1 P 0 C in C 2 = G 2 + P 2 C 1 = G 2 + G 1 P 2 + G 0 P 2 P 1 + P 2 P 1 P 0 C in =G 2:1 +P 2:1 C 0 (G 2:1 =G 2 +P 2 G 1 P 2:1 =P 2 P 1 ) C 3 = G 3 + P 3 C 2 = G 3 + G 2 P 3 + G 1 P 3 P 2 + G 0 P 3 P 2 P 1 + P 3 P 2 P 1 P 0 C in =G 3:2 +P 3:2 C 1 =G 3:2 +P 3:2 (G 1:0 +P 1:0 C 0 )=(G 3:2 +P 3:2 G 1:0 )+P 3:2 P 1:0 C 0 G 3:2 =(G 3 +P 3 G 2 ) and P 3:2 =P 3 P 2 are called dot products.

32. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 32 Tree Adders 16-bit radix-2 Kogge-Stone tree (radix 2 means that the tree is Binary: it combines two dot product or carry words at a time at Each level of hierarchy)

33. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 33 Tree Adders 16-bit radix-4 Kogge-Stone Tree

34. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 34 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

35. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 35 Tree Adders Brent-Kung Tree

36. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 36 Intel Itanium Microprocessor Itanium has 6 integer execution units like this

37. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 37 Bit-Sliced Design

38. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 38 Bit-Sliced Datapath The adder is implemented as a radix-4 Carry Look- Ahead adder, the red lines are forwarding the results of different stages

39. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 39 Itanium Integer Datapath Courtesy of Intel

40. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 40 Multipliers

41. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 41 The Binary Multiplication

42. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 42 The Binary Multiplication

43. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 43 The Array Multiplier (4 by 4) The carryout of the last adder for Y i is forwarded to Y i+1 carry sum Half adder

44. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 44 The MxN Array Multiplier — Critical Path Critical Path 1 & 2

45. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 45 Carry-Save Multiplier  A more efficient realization can be obtained by noticing that the multiplication results does not change when the output carry bits are passed diagonally downwards instead of to the right.  But need extra adders (vector merging adders) that can use fast carry look ahead adders (since results come at the same time)  Critical path is uniquely defined

46. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 46 Multiplier Floorplan

47. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 47 Wallace-Tree Multiplier Save the number of full adders Increase the complexity of routing

48. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 48 Wallace-Tree Multiplier HA Can use carry Look-Ahead adder for the last stage

49. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 49 Wallace-Tree Multiplier

50. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 50 Booth encoding  Multiply by 01111110 gives 8 partial products, but two are all zero. Add these zero is waste of time.  Instead, multiply by 100000010, where 1 stands for -1. Then you need to only add (actually subtract) partial products, which improves speed  This kind of transformation is called booth encoding. It reduces the number of partial product to at most half of the original multiplier width.  The encoding logic is easily incorporated in the overall multiplier design.

51. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 51 Multipliers —Summary This is also why algorithmic invention has significant meaning to VLSI design.

52. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 52 Shifters

53. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 53 The Binary Shifter

54. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 54 The Barrel Shifter Area Dominated by Wiring Column: maximum shift Word length

55. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 55 4x4 barrel shifter  Coder/decoder required to set shift bits  Signal pass through one gate independent of shift amount (parasitic capacitance may change the picture)

56. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 56 Logarithmic Shifter No separate coder/decoder is required

57. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 57 A 3 A 2 A 1 A 0 Out3 Out2 Out1 Out0 0-7 bit Logarithmic Shifter Good for large shift amount (note that cascade pass transistor slow down the gate and generate weak signals, buffers may be needed)

58. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 58 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator) (comparator, divider, sin, cos etc)