2. Ch3b- 2 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University There is logic to it andRd, Rs, RtRd <-- Rs Rt orRd, Rs, RtRd <-- Rs  Rt AND, OR are bitwise logic operations 0010 0011 0111 0110 1010 1111 0000 1101 OR 1001 1010 1000 0101 0001 1011 1010 0011 Example: Set bit 7 of $s9 to ‘1’ (Don’t mess with the other 31 bits) ori$s9, $s9, 0x0080 0x0080 = 0000 0000 1000 0000 Example: Clear bit 14 of $t3 to ‘0’ andi$t3, $t3, 0xBFFF 0xBFFF = 1011 1111 1111 1111 Note: Bit numbering starts at zero. 1011 1011 1111 0111 1011 1111 1010 1111

3. Ch3b- 3 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Shifty Instructions Shift instructions scoot all the bits in a register over sll$s3, $t2, 1# $s3 <-- $t2 shifted left 1 bit 0010 0011 0111 0110 1010 1111 0000 1101 $t2 0100 0110 1110 1101 0101 1110 0001 101 $s3 Old MSB: Bit-bucketed New LSB: Zero srl$t3, $s4, 5# $t3 <-- $s4 right shifted 5 bits 0 Opcode RS RT RD ShAmt Function R-Type Instruction 0

4. Ch3b- 4 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Using Shifts 1. You need only the 2nd byte of a 4-byte word srl $t1, $t1, 8 0010 0011 0111 0110 1010 1111 0000 1101 $t1 0000 0000 0010 0011 0111 0110 1010 1111 $t1 andi $t1, $t1, 0x00FF 0000 0000 0000 0000 0000 0000 1010 1111 $t1 2. You want to multiply $t3 by 8 (note: 8 equals 2 3 ) 0000 0000 0000 0000 0000 0000 0000 0101 $t3 sll $t3, $t3, 3# move 3 places to the left 0000 0000 0000 0000 0000 0000 0010 1000 $t3 (equals 5) (equals 40) To access only part of a word, we need the bits on the RHS 8 0000 0000 0000 0000 0000 0000 1111 1111 Note - extended with 16 0’s Must isolate only the 8 bits on RHS

5. Ch3b- 5 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Arithmetic and Logic Unit The ALU is at the heart of the CPU Does math and logic The ALU is primarily involved in R-type instructions Perform an operation on two registers and produce a result Where is the operation specified? The instruction type specifies the operation The ALU will have to be controlled by the instruction opcode

6. Ch3b- 6 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Constructing an ALU - Logic Operations 0 1 A B Operation Result 2-to-1 Mux If Operation = 0, Result = A B If Operation = 1, Result = A  B Start out by supporting AND and OR operations AB A+B Two operands, two results. We need only one result... The Operation input comes from logic that looks at the opcode

7. Ch3b- 7 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Half Adder AiAi 0 0 1 1 Sum 0 1 1 0 CarryOut 0 0 0 1 1 BiBi 0 0 1 Sum = A i B i  A i B i = A i  B i CarryOut = A i B i CarryOut Sum A i B i + A half adder adds two bits, A and B and produces a Sum and CarryOut Sum CarryOut A i B i Problem: We often need to add two bits and a CarryIn...

8. Ch3b- 8 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Full Adder B AB 00011110 0 1 A C in C out 0 0 0 1 1 1 0 1 B AB 00011110 0 1 A C in Sum 0 1 1 0 0 1 1 0 C out = Sum = A  B  C in + B1B1 A1A1 Sum CarryOut CarryIn A full adder adds two bits, A and B, and a CarryIn and produces a Sum and CarryOut ABC in C out Sum 00000 00101 01001 01110 1 0001 10110 11010 11111  BC in  AC in AB

9. Ch3b- 9 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Adding to our ALU CarryIn CarryOut ALU A B C out C in Result C in C out Op (2 bits) OperationFunction 00A B 01A  B 10A + B OperationFunction 00A B 01A  B 10A + B + (Op is now 2 bits) Add an Adder Connect CarryIn (from previous bit) and CarryOut (to next bit) Expand Mux to 3-to-1 (Op is now 2 bits) 0 1 Operation Result A B 2 0 1

10. Ch3b- 10 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Putting it all together C in A0A0 B0B0 Result 0 ALU 0 C in C out Operation A1A1 B1B1 Result 1 ALU 1 C in C out A2A2 B2B2 Result 2 ALU 2 C in C out A 31 B 31 Result 31 ALU 31 C in C out Connect to common Operation controls Now we can do 32-bit AND and OR operations Stack 32 of our 1-bit ALU’s together Each one gets one bit from A and one from B Connect C out ’s to C in ’s Now, 32-bit adds will work Note: Carry will ripple through the stages, one at a time Ripple-Carry Adder

11. Ch3b- 11 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Subtracting 0 1 B 0 1 A Operation Result + 2 CarryIn CarryOut BInvert For subtraction: Set Carry In of LSB to 1, Set BInvert to 1 For subtraction: Set Carry In of LSB to 1, Set BInvert to 1 Add an inverter, and a signal BInvert to get B Now, how about that +1? Carry In to LSB is unused (always zero) Set it to 1! Subtraction just sets BInvert and C in to 1 B Our ALU can add now, but what about subtraction? To compute A - B, we can instead compute A + (-B) In 2’s complement, -B = B + 1 Set to 1 for LSB

12. Ch3b- 12 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University Support for SLT A<B is equivalent to (A - B) < 0 Subtract B from A If the result is negative, then set LSB of Result to ‘1’, all others to ‘0’ The result is negative if the MSB after the subtraction is ‘1’ (Two’s complement) Result 0 1 A Operation + 2 B CarryIn CarryOut 0 1 BInvert Less We’re going to have to do something different for the MSB and the LSB We need to support the SLT operation Set Result to 0000 0000 0000 0000 0000 0000 0000 0001 if A <B 0 1 2 3 Less will be ‘0’ for bits 1-31, special for bit 0

13. Ch3b- 13 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University That tricky MSB To properly execute the SLT, we need to Set the LSB if the MSB is ‘1’ (After a subtraction) OverFlow Set 0 1 A Operation Result + 2 B CarryIn CarryOut 0 1 BInvert 3 Less MSB Only Can’t use the ‘Result’ of the MSB Op will set the Mux to the ‘Less’ Field Bring out the adder output directly: ‘Set’ Also, we need to check for overflow Overflow if C in to MSB is different from C out of MSB

14. Ch3b- 14 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University C in Operation C out Our new and improved 32-bit ALU The Whole Thing BInvert 0 ALU 31 Result 31 C in A 31 B 31 C out Less OverFlow Set Add the BInvert control to each bit Connect ‘Set’ output of MSB to ‘Less’ Input of LSB Set the LSB during SLT when negative Output OverFlow from MSB ALU 0 A0A0 B0B0 Result 0 C in Less C out 0 B2B2 ALU 2 Result 2 C in A2A2 Less C out 0 ALU 1 Result 1 A1A1 B1B1 C out Less C in Connect ‘0’ to all the Less inputs except LSB

15. Ch3b- 15 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University One Last Change Zero A B Result OverFlow Operation C out Result 2 Result 1 C in Operation C out BInvert 0 OverFlow Set 0 0 ALU 31 Result 31 C in A 31 B 31 C out Less ALU 0 A0A0 B0B0 Result 0 C in Less C out B2B2 ALU 2 C in A2A2 Less C out ALU 1 A1A1 B1B1 C out Less C in We need to add a check to see if the result is zero

16. Ch3b- 16 EE/CS/CPE 3760 - Computer Organization  Seattle Pacific University ALU Functions Function BInvOpCarry in Result And0000R = A B Or0010 R = A  B Add0100R = A + B Subtract1101R = A - B SLT1111R = 1 if A < B 0 if A  B Function BInvOpCarry in Result And0000R = A B Or0010 R = A  B Add0100R = A + B Subtract1101R = A - B SLT1111R = 1 if A < B 0 if A  B 0 1 A Operation Result + 2 B Carry In Carry Out 0 1 BInvert 3 Less We also have zero-detect for BEQ, BNE (use subtract). Skipping over Shift operations... Note: Adding would be a lot faster if we didn’t use a ripple- carry adder... Since Binvert and Carryin are always the same, we can combine them in to a single signal subtract