1. Lecture 4. Adder & Subtractor Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research

2. Korea Univ Arithmetic Circuits Arithmetic circuits are the central building blocks of computers (CPUs) Computers are able to perform many arithmetic functions such as addition, subtraction, comparison, shift, multiplication, and division We are going to study hardware implementations of these operations Let’s start with adder Addition is one of most common operations in computer 2

3. Korea Univ 1-bit Half Adder Let’s first consider how to implement an 1-bit adder Half adder  2 inputs: A and B  2 outputs: S (Sum) and C out (Carry) 3 ABS(um)C(arry) 00 01 10 11 A B Sum Carry 00 10 0 0 1 1

4. Korea Univ 1-bit Full Adder Half adder lacks a C in input to accept C out of the previous column Full adder  3 inputs: A, B, C in  2 outputs: S, C out 4 CinABS(um)C out 000 001 010 011 100 101 110 111 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0

5. Korea Univ 1-bit Full Adder 5 CinABS(um)C out 00000 00110 01010 01101 10010 10101 11001 11111 00011110 0 0101 1 1010 Cin AB 00011110 0 0010 1 0111 Cin AB 00011110 0 0010 1 0111 Cin AB or Slide from Prof. Sean Lee, Georgia Tech Sum C out

6. Korea Univ 1-bit Full Adder Schematic 6 A B C in C out S Half Adder Slide from Prof. Sean Lee, Georgia Tech

7. Korea Univ Multi-bit Adder It seems that an 1-bit adder is doing not much of work Let’s move on to a multi-bit adder  N-bit adder sums two N-bit inputs (A and B), and C in (carry-in) It is commonly called carry propagate adders (CPAs) because the carry-out of one bit propagates into the next bit Three common CPA implementations  Ripple-carry adders (slow)  Carry-lookahead adders (fast)  Prefix adders (faster) 7

8. Korea Univ Ripple-Carry Adder The simplest way to build an N-bit CPA is to chain 1- bit adders together  Carry ripples through entire chain 8 Example: 32-bit Ripple Carry Adder

9. Korea Univ 4-bit Ripple-Carry Adder 9 Full Adder AB Cin Cout S S0 A0B0 Full Adder AB Cin Cout S S1 A1B1 Full Adder AB Cin Cout S S2 A2B2 Full Adder AB Cin Cout S S3 A3B3 Carry S0 Modified from Prof Sean Lee’s Slide, Georgia Tech A B C in S C out

10. Korea Univ Delay of Ripple Carry Adder 10 S0 A0B0 Carry Cin 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR Slide from Prof. Sean Lee, Georgia Tech

11. Korea Univ Delay of Ripple Carry Adder 11 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR 2 nd Stage Critical Path = 2 gate delays = D AND +D OR (Assume that inputs are applied at the same time) S0 A0B0 Cin S1 A1B1 Slide from Prof. Sean Lee, Georgia Tech

12. Korea Univ Delay of Ripple Carry Adder 12 Critical path delay of a 4-bit ripple carry adder D XOR + 4 (D AND +D OR ) : 9 gates delay Critical path delay of an N-bit ripple carry adder  2(N-1)+3 = (2N+1) gate delays S0 A0B0 Cin S1 A1B1 S2 A2B2 S3 A3B3 Carry Modified from Prof Sean Lee’s Slide, Georgia Tech

13. Korea Univ Ripple-Carry Adder Delay Ripple-carry adder has disadvantage of being slow when N is large  The delay of an N-bit ripple-carry adder is roughly t ripple = N t FA (t FA is the delay of a full adder) A faster adder needs to address the serial propagation of the carry bit 13

14. Korea Univ Carry-Lookahead Adder The fundamental reason that large ripple-carry adders are slow is that the carry signals must propagate through every bit in the adder A carry-lookahead adder (CLA) is another type of CPA that solves this problem.  It divides the adder into blocks and provides circuitry to quickly determine the carry out of a block as soon as the carry-in is known 14

15. Korea Univ Carry-Lookahead Adder Compute the carry-out (C out ) for an N-bit block  Compute generate (G) and propagate (P) signals for columns and then an N-bit block  A column (bit i) can produce a carry-out by either generating a carry- out or propagating a carry-in to the carry-out Generate (G i ) and Propagate (P i ) signals for each column  A column will generate a carry-out if both A i and B i are 1 G i = A i B i  A column will propagate a carry-in to the carry-out if either A i or B i is 1 P i = A i + B i Express the carry-out of a column (C i ) in terms of P i and G i C i = A i B i + (A i + B i )C i-1 = G i + P i C i-1 15

16. Korea Univ Carry Generate & Propagate 16 What do these equations mean? Let’s think about these equations for a moment Modified from Prof H.H.Lee’s Slide, Georgia Tech g i = A i B i p i = A i + B i C i = A i B i + (A i + B i ) C i-1 C i = g i + p i C i-1 C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1

17. Korea Univ Carry Generate & Propagate A 4-bit block will generate a carry-out if column 3 generates ( g 3 ) a carry or if column 3 propagates ( p 3 ) a carry that was generated or propagated in a previous column G 3:0 = g 3 + p 3 (g 2 + p 2 (g 1 + p 1 g 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 A 4-bit block will propagate a carry-in to the carry-out if all of the columns propagate the carry P 3:0 = p 3 p 2 p 1 p 0 We compute the carry out of the 4-bit block (C i ) as C i = G i:j + P i:j C j 17

18. Korea Univ 4-bit CLA 18 Carry Lookahead Logic g1p1 A1B1 S1 C0 g2p2 A2B2 S2 C1 g3p3 A3B3 S3 C2 g0p0 A0B0 S0 C -1 C3 Slide from Prof. Sean Lee, Georgia Tech

19. Korea Univ An Implementation of CLA 19 A0B0S0A1B1S1A2B2S2A3B3 S3  Carry Delay is 4*D AND + 2*D OR for Carry C 3  Reuse some gate output results in little Improvement C -1 Slide from Prof. Sean Lee, Georgia Tech C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1

20. Korea Univ More Expensive and Fast CLA 20 Carry Lookahead Logic C3 A0B0S0A1B1S1 C -1 A2B2S2A3B3 S3 Only 3 Gate Delay for each Carry C i = D AND + 2*D OR Slide from Prof. Sean Lee, Georgia Tech C 0 = g 0 + p 0 C -1 C 1 = g 1 + p 1 C 0 = g 1 + p 1 g 0 + p 1 p 0 C -1 C 2 = g 2 + p 2 C 1 = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 C -1 C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1

21. Korea Univ 32-bit CLA with 4-bit blocks 21 It shows a path to C3 only C 3 = g 3 + p 3 C 2 = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 C -1

22. Korea Univ CLA Delay The delay of an N-bit CLA with k-bit blocks is roughly: t CLA = t pg + t pg_block + (N/k – 1)t AND_OR + kt FA where  t pg is the delay of the column generate and propagate gates  t pg_block is the delay of the block generate and propagate gates  t AND_OR is the delay from C in to C out of the final AND/OR gate 22 t pg t pg_block t AND_OR

23. Korea Univ Adder Delay Comparisons Compare the delay of 32-bit ripple-carry adder and CLA  The CLA has 4-bit blocks  Assume that each two-input gate delay is 100 ps  Assume that a full adder delay is 300 ps t ripple = Nt FA = 32(300 ps) = 9.6 ns t CLA = t pg + t pg_block + (N/k – 1)t AND_OR + kt FA = [100 + 600 + (7)200 + 4(300)] ps = 3.3 ns 23

24. Korea Univ Verilog-HDL Representation 24 module adder #(parameter N = 8) (input [N-1:0] a, b, input cin, output [N-1:0] s, output cout); assign {cout, s} = a + b + cin; endmodule

25. Korea Univ Then, When to Use What? We have discussed 3 kinds of CPA  Ripple-carry adder  Carry-lookahead adder  Prefix adder (see backup slides) Faster adders require more hardware and therefore they are more expensive and power-hungry So, depending on your speed requirement, you can choose the right one If you use HDL to describe an adder, the CAD tools will generate appropriate logic considering your speed requirement 25

26. Korea Univ References Our book covers very little about addition and subtraction Refer to the following books for details  Logic and Computer Design Fundamentals by Morris Mano, 4 th edition (Ch 4. Arithmetic Functions and HDLs, pp 168 ~ pp 185) 26

27. Korea Univ Revisiting 2’s Complement Number Given an n-bit number N, the 2s complement of N is defined as 2 n – N for N ≠ 0 0 for N = 0  Example: 3 is 4’b0011 (in a 4-bit binary) 2s complement of 3: 2 4 -3 = 4’b1101 A fast way to get a 2s complement number is to flip all the bits and add 1 In hardware design of computer arithmetic, the 2s complement number provides a convenient and simple way to do addition and subtraction of unsigned and signed numbers 27

28. Korea Univ Subtractor Suppose that we use a 4-bit 28 7 - 5 0111 0101 3 - 7 0011 0111 Result = 2Result = -4 0111 + 1011 10010 0011 + 1001 01100 C in C out

29. Korea Univ An Implementation of a 4-bit Adder and Subtractor 29 Full Adder AB Cin Cout S S0 A0 Full Adder AB Cin Cout S S1 A1 Full Adder AB Cin Cout S S2 A2 Full Adder AB Cin Cout S S3 A3 B0B1B2B3 C Subtract Hmmm.. So, it looks simple! Are we done?Not Really!!

30. Korea Univ Subtraction of Unsigned Numbers Unsigned number is either positive or zero  There is no sign bit  So, a n-bit can represent numbers from 0 to 2 n - 1 For example, a 4-bit can represent 0 to 15 (=2 4 – 1)  To declare an unsigned number in C language, unsigned int a;  x86 allocates a 32-bit for a variable of unsigned int Subtraction of unsigned integers  M – N in binary can be done as follows: M + (2 n – N) = M – N + 2 n If M ≥ N, the sum does produce an end carry, which is 2 n  Subtraction result is zero or a positive number If M < N, the sum does not produce an end carry since it is equal to 2 n – (N – M) Unsigned Underflow  If there is no carry-out from adder, the subtraction result is negative (and unsigned number can’t represent negative numbers) 30

31. Korea Univ Example Suppose that we use a 4-bit (0 ~ 15) 31 10 - 5 1010 0101 #include void main() { unsigned int ua, ub, uc; ua = 10; ub = 5; uc = ua - ub ; printf("hex: ua = h'%x, ub = h'%x, uc = h'%x\n", ua, ub, uc); printf("unsigned: ua = d'%u, ub = d'%u, uc = d'%u\n", ua, ub, uc); printf("signed: ua = d'%d, ub = d'%d, uc = d'%d\n", ua, ub, uc); } 1010 + 1011 10101 Carry-out can be used in comparison of two unsigned numbers If the sum produces an end carry, then the minuend (10) is equal to the subtrahend (5) or larger than the subtrahend

32. Korea Univ Another Example Suppose that we use a 4-bit (0 ~ 15) 32 10 - 13 1010 1101 #include void main() { unsigned int ua, ub, uc; ua = 10; ub = 13; uc = ua - ub ; printf("hex: ua = h'%x, ub = h'%x, uc = h'%x\n", ua, ub, uc); printf("unsigned: ua = d'%u, ub = d'%u, uc = d'%u\n", ua, ub, uc); printf("signed: ua = d'%d, ub = d'%d, uc = d'%d\n", ua, ub, uc); } 1010 + 0011 01101 It is called unsigned underflow (borrow) when the carry out is 0 in unsigned subtraction Carry-out can be used in comparison of two unsigned numbers If the sum does not produces an end carry, then the former (10) is smaller the latter (13) Be careful when you do your programming Understand the consequence of the execution of your program in computer!!!

33. Korea Univ Subtraction of Signed Numbers Signed number represents positive or negative number  There is a sign bit (MSB)  A n-bit can represent numbers from -2 n-1 to 2 n-1 -1 For example, a 4-bit can represent -8 (-2 3 ) to 7 (=2 3 – 1)  To declare a signed number in C language, int a; // signed is implicit  x86 allocates a 32-bit for a variable of signed int Subtraction of signed integers  It is simply done by addition of two binary numbers in 2s complement form A carry-out from the sign bit position is discarded 33

34. Korea Univ Example Suppose that we use a 4-bit (-8 ~ 7) 34 7 - 5 0111 0101 #include void main() { int sa, sb, sc; sa = 7; sb = 5; sc = sa - sb ; printf("hex: sa = h'%x, sb = h'%x, sc = h'%x\n", sa, sb, sc); printf("unsigned: sa = d'%u, sb = d'%u, sc = d'%u\n", sa, sb, sc); printf("signed: sa = d'%d, sb = d'%d, sc = d'%d\n", sa, sb, sc); } 0111 + 1011 10010

35. Korea Univ Example Suppose that we use a 4-bit (-8 ~ 7) 35 5 - 7 0101 0111 #include void main() { int sa, sb, sc; sa = 5; sb = 7; sc = sa - sb ; printf("hex: sa = h'%x, sb = h'%x, sc = h'%x\n", sa, sb, sc); printf("unsigned: sa = d'%u, sb = d'%u, sc = d'%u\n", sa, sb, sc); printf("signed: sa = d'%d, sb = d'%d, sc = d'%d\n", sa, sb, sc); } 0101 + 1001 01110

36. Korea Univ Overflow/Underflow  The answer to an addition or subtraction exceeds the magnitude that can be represented with the allocated number of bits Overflow/Underflow is a problem in computers because the number of bits to hold a number is fixed  For this reason, computers detect and flag the occurrence of an overflow/underflow Detection of an overflow/underflow after the addition of two binary numbers depends on whether the numbers are considered to be signed or unsigned 36

37. Korea Univ Overflow/Underflow in Unsigned Numbers When two unsigned numbers are added, overflow is detected from the end carry-out of the most significant position  If the end carry is 1, there is an overflow When two unsigned numbers are subtracted, underflow is detected when the end carry is 0 37

38. Korea Univ Overflow/Underflow in Signed Numbers With signed numbers, an overflow/underflow can’t occur for an addition if one number is positive and the other is negative.  Adding a positive number to a negative number produces a result whose magnitude is equal to or smaller than the larger of the original numbers An overflow may occur in addition if two numbers are both positive  When x and y both have sign bits of 0 (positive numbers) If the sum has sign bit of 1, there is an overflow An underflow may occur in addition if two numbers are both negative  When x and y both have sign bits of 1 (negative numbers) If the sum has sign bit of 0, there is an underflow 38

39. Korea Univ Examples 39 01001000 (+72) 00111001 (+57) -------------------- 10000001 (+129) What is largest positive number represented by 8-bit? 8-bit Signed number addition 10000001 (-127) 11111010 ( -6) -------------------- 01111011 (-133) 8-bit Signed number addition What is smallest negative number represented by 8-bit?

40. Korea Univ Overflow/Underflow in Signed Numbers We can detect overflow/underflow with the following logic  Suppose that we add two k-bit numbers x k-1 x k-2 … x 0 + y k-1 y k-2 … y 0 = s k-1 s k-2 … s 0 There is an easier formula  Let the carry out of a k-bit full adder be c k-1 c k-2 … c 0  If a 0 ( c k-2 ) is carried in, the only way that 1 ( c k-1 ) can be carried out is when x k-1 = 1 and y k-1 = 1 (Adding two negative numbers results in a non-negative number)  If a 1 ( c k-2 ) is carried in, the only way that 0 ( c k-1 ) can be carried out is when x k-1 = 0 and y k-1 = 0 (Adding two positive numbers results in a negative number) 40 Overflow = x k-1 y k-1 s k-1 + x k-1 y k-1 s k-1 Overflow = c k-1 + c k-2

41. Korea Univ Overflow/Underflow Detection of Signed Numbers 41 Full Adder AB Cin Cout S S0 A0B0 Full Adder AB Cin Cout S S1 A1B1 Full Adder AB Cin Cout S S2 A2B2 Full Adder AB Cin Cout S S3 A3B3 Carry Overflow/ Underflow n-bit Adder/Subtractor Overflow/ Underflow C n-1 C n-2 Prof. Sean Lee’s Slide, Georgia Tech

42. Korea Univ Recap Unsigned numbers  Overflow could occur when 2 unsigned numbers are added An end carry of 1 indicates an overflow  Underflow could occur when 2 unsigned numbers are subtracted An end carry of 0 indicates an underflow (minuend < subtrahend) Signed numbers  Overflow could occur when 2 signed positive numbers are added  Underflow could occur when 2 signed negative numbers are added  Overflow flag (C n-1 ^ C n-2 ) indicates either overflow or underflow 42

43. Korea Univ Recap Binary numbers in 2s complement system are added and subtracted by the same basic addition and subtraction rules as used in unsigned numbers  Therefore, computers need only one common hardware circuit to handle both types (signed, unsigned numbers) of arithmetic The programmer must interpret the results of addition or subtraction differently, depending on whether it is assumed that the numbers are signed or unsigned 43

44. Korea Univ 44 Backup Slides

45. Korea Univ Prefix Adder Computes generate and propagate signals for all of the columns (!) to perform addition even faster Computes G and P for 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the generate and propagate signals are known for each column  Then, the prefix adder has log 2 N stages The strategy is to compute the carry in (C i-1 ) for each of the columns as fast as possible and then to compute the sum: S i = (A i  B i )  C i-1 45

46. Korea Univ Prefix Adder A carry is generated by being either generated in a column or propagated from a previous column Define column -1 to hold C in, so G -1 = C in, P -1 = 0 Then, C i-1 = G i-1:-1 because there will be a carry out of column i-1 if the block spanning columns i-1 through -1 generates a carry Thus, we can rewrite the sum equation as: S i = (A i  B i )  G i-1:-1 46

47. Korea Univ Prefix Adder The generate and propagate signals for a block spanning bits i:j are G i:j = G i:k  P i:k G k-1:j P i:j = P i:k P k-1:j These signals are called the prefixes because they must be precomputed before the final sum computation can complete In words, these prefixes describe that  A block will generate a carry if the upper part (i:k) generates a carry or the upper part propagates a carry generated in the lower part (k-1:j)  A block will propagate a carry if both the upper and lower parts propagate the carry. 47

48. Korea Univ 4-bit Prefix Adder 48 B3B3 B2B2 B1B1 B0B0 A3A3 A2A2 A1A1 A0A0 C in G -1 = C in, P -1 = 0 P 2, G 2 P 1, G 1 P 0, G 0 P -1, G -1 P i = A i B i, G i = A i + B i P 0:-1, G 0:-1 P 2:1, G 2:1 P 2:1 = P 2 P 1, G 2:1 = G 2 + P 2 G 1 P 0:-1 = P 0 P -1, G 0:-1 = G 0 + P 0 G -1 S3S3 S2S2 S1S1 S0S0 S 3 = A 3 B 3 G 2:-1 S 2 = A 2 B 2 G 1:-1 S 1 = A 1 B 1 G 0:-1 S 0 = A 0 B 0 G -1 + + + + + + + + P 2:-1, G 2:-1 P 2:-1 = P 2:1 P 0:-1, G 2:-1 = G 2:1 + P 2:1 G 0:-1 P 1:-1, G 1:-1 P 1:-1 = P 1 P 0:-1, G 1:-1 = G 1 + P 1 G 0:-1 C -1 = G -1 C 0 = G 0:-1 C 1 = G 1:-1 C 2 = G 2:-1 Remember that P 2:-1 is always “0” since P -1 = 0, but intermediate propagate signals (P 1:-1, P 0:-1, P 2:1 ) are used for calculating subsequent generate signals

49. Korea Univ 16-bit Prefix Adder 49 G -1 = C in, P -1 = 0

50. Korea Univ Prefix Adder Delay The delay of an N-bit prefix adder is: t PA = t pg + log 2 N(t pg_prefix ) + t XOR where  t pg is the delay of the column generate and propagate gates  t pg_prefix is the delay of the black prefix cell 50

51. Korea Univ Flags in CPU In general, computer has several flags (registers) to indicate state of operations such as addition and subtraction  N: Negative  Z: Zero  C: Carry  V: Overflow We have only one adder inside a computer  CPU does comparison of signed or unsigned numbers by subtraction using adder  Computer sets the flags depending on the operation result  Then, do these flags provide enough information to judge that one is bigger than or less than the other? 51

52. Korea Univ Example 52 void example(void) { unsigned int a, b, c; signed int aa, bb, cc; a = 0x10; b = 0x20; aa = 0x30; bb = 0x40; if (a > b) c = a + b; else c = a - b; if (aa > bb) cc = aa + bb; else cc = aa - bb; return; } Equality  a == b ? Do subtraction True if the Z flag is set Unsigned number comparison  a > b ? Do subtraction True if C is set and Z is clear Signed number comparison  a > b ? Do subtraction True if N == V, meaning either  Both N and V are set (1) or  Both N and V are clear (0)

53. Korea Univ Example 53 Signed number comparison  a > b ? Do subtraction True if N == V, meaning either  Both N and V are set (1) or  Both N and V are clear (0) 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 N == V Both are 0, meaning that overflow didn’t happen Examples: 5 – 1, 3 – (-4), (-3) – (-4) Both are 1, meaning that overflow did happen Examples: 5 – (-3), 7 – (-4)

54. Korea Univ EFLGAS in x86 54

55. Korea Univ EFLGAS in x86 55

56. Korea Univ CPSR in ARM 56

57. Korea Univ CPSR in ARM 57