1. Wrapper/TAM Optimization1 System-on-Chip (SoC) Testing SoC Wrapper/TAM Design

2. Wrapper/TAM Optimization2 Scan Chain Architectures* * J. Aerts and E. J. Marinissen, ITC 1998, pp. 448-457

3. Wrapper/TAM Optimization3 Paper Summary Given: # pins SoC available for external scan test # scan patterns of each core # scan FFs in each core the paper explores the pros and cons of three possible scan-chain architectures for testing the SoC with external source and sink.

4. Wrapper/TAM Optimization4 Three Basic Scan Architectures 1. Multiplexing: Whole TAM width available to each core, but one at a time. 2. Daisychain: Long chains across multiple cores simultaneously test multiple cores, bypassing those for which the testing is completed. 3. Distribution: Test many cores concurrently but by dividing the TAM lines among them.

5. Wrapper/TAM Optimization5 Multiplexing Architecture - 1 Full TAM width available to each core exclusively DeMux/Mux at inputs and outputs are necessary to connect TAM lines to core pins. Each parallel scan chain requires two signals: scan- in and scan-out. Additionally, at least two global signals are necessary to control scan- enable and mux/demux

6. Wrapper/TAM Optimization6 Multiplexing Architecture - 2 # scan chains available: where, K = # pins available for scan test M = number of control pins (= 2) Total test time, overlapping scan-in and scan-out:

7. Wrapper/TAM Optimization7 Daisychain Architecture A 2-to-1 mux after each core selects either the core’s internal scan chain or the (buffered) bypass One test Strategy: Use daisy chain to transport patterns to all cores at once, until a core runs out of patterns and is bypassed. Other test strategies are also possible

8. Wrapper/TAM Optimization8 Distribution Architecture Distribute the scan chains over the cores Each core gets assigned its own dedicated scan chains The number of scan chains must exceed the number of cores.

9. Wrapper/TAM Optimization9 Hybrid Architectures Test-Bus 1 : Combines multiplexing and distribution. TestRail 2 : Combines daisychain and distribution. 1. P. Varma and S. Bhatia, ITC98, pp. 294- 302. 2. E. J. Marinissen et al., ITC98, pp. 284-293.

10. Wrapper/TAM Optimization10 Test Wrapper and TAM Co- Optimization for SoC V. Iyengar, K. Chakrabarty, and E. J. Marinissen, JETTA 18, March 2002, pp. 211-228

11. Wrapper/TAM Optimization11 Paper Summary Simultaneous design of wrapper and TAM to optimize the testing times for cores. Algorithm improves on earlier methods of wrapper design in reducing the TAM width required to achieve optimum test time. Another enumerative algorithm for TAM optimization for small number of TAMs.

12. Wrapper/TAM Optimization12 Example SoCs - 1 (from ISCAS Benchmarks)

13. Wrapper/TAM Optimization13 Example SoCs – 2 (From Philips Research)

14. Wrapper/TAM Optimization14 Unbalanced vs. Balanced Wrapper Chains UnbalancedBalanced The time is minimized for balanced cores. 14 clocks/scan 8 clocks/scan

15. Wrapper/TAM Optimization15 Wrapper Design Example without and with Co-optimization Assume: Available TAM Width: 4 4 inputs 2 outputs 4 scan chains: 32, 8, 8, 8 long Clearly, (b) utilizes TAM width better than (a)

16. Wrapper/TAM Optimization16 Longest Wrapper Scan-in (Scan-out) vs. TAM Width Problem: Given the following internal scan chain lengths, plot the longest wrapper scan length as a function of TAM width k for k = 1, 2, 3, 4, 5, 6. Given scan chain lengths: 8, 8, 8, 8, 8, 10, 10, 10.

17. Wrapper/TAM Optimization17 Example of a Philips’ p93791 core This core has: 417 functional inputs 324 functional outputs 72 bidirectional I/Os 46 scan chains of lengths: 7x500 bits 30x520 bits 9x521 bits Example Pareto- optimal point

18. Wrapper/TAM Optimization18 Two-Priority Wrapper Optimization Problem: Formal Statement The paper provides an approximation algorithm based on the Best Fit Decreasing (BFD) heuristic to solve the problem.

19. Wrapper/TAM Optimization19 Algorithm

20. Wrapper/TAM Optimization20 Example Core and Result

21. Wrapper/TAM Optimization21 Optimal Core Assignment to TAMs Test Bus Model for TAM Design: Cores on each TAM are sequentially tested Test Bus Model for TAM Design Multiplexed CoresCores with Bypass

22. Wrapper/TAM Optimization22 Problem Definition Minimize the system test time by assigning cores to TAMs when the TAM widths are known: An integer linear programming (ILP) based algorithm is presented in the paper to solve small instances of the problem.

23. Wrapper/TAM Optimization23 Results for SoC from ISCAS Benchmarks -1

24. Wrapper/TAM Optimization24 Generalizations - 1 The paper goes on to solve the following generalizations of the problems discussed so far: Optimal Partitioning of TAM Widths:

25. Wrapper/TAM Optimization25 Generalizations - 2 Wrapper/TAM Co-Optimization

26. Wrapper/TAM Optimization26 Results for SoC from ISCAS Benchmarks -2