1. Kevin Pitts February 24, 2000 XTRP Review slide - 1 XTRP Review Agenda: äIntroduction/OverviewK. Pitts10’ äBoard StatusM. Kasten25’ äDAQ/Interface/Test Software N. Eddy15’ äMap Generation/Implementation H. Kim15’ äSchedule/SummaryPitts/Kasten XTRP Group: Nathan Eddy, Lee Holloway, Mike Kasten, Hyunsoo Kim, Kevin Pitts Documentation: http://web.hep.uiuc.edu/Engin/CDF/XTRP/

2. Kevin Pitts February 24, 2000 XTRP Review slide - 2 People Involved l Mike Kasten älead engineer: board design/fab/testing l Nathan Eddy äpostdoc: DAQ/testing software, Java-man l Hyunsoo Kim äpostdoc: map generation/implementation; interface with database and front end; offline simulation l Kevin Pitts äspiritual guidance: Spirit? Maybe. Guidance? Not much. Knowledge? None. l Plan to add a grad student very soon

3. Kevin Pitts February 24, 2000 XTRP Review slide - 3 Trigger l XTRP is the interface between tracks in the COT (XFT) and the remainder of the Level 1 trigger. l XFT data input to the XTRP l Output info to: äL1 calorimeter (extrapolate) äL1 muon (extrapolate) äTrack Trigger (pass) äGlobal L1 & L2 (pass) äSVT (pass)

4. Kevin Pitts February 24, 2000 XTRP Review slide - 4 XTRP Overview l XTRP system: ä1 clock/control board ä1 clock/control transition module ä12 data boards ä12 data board transition modules l Entire system: one VME crate äVIPA-style (not CDF-style) äP2 not bussed älocation: 2nd floor trigger room

5. Kevin Pitts February 24, 2000 XTRP Review slide - 5 XTRP System

6. Kevin Pitts February 24, 2000 XTRP Review slide - 6 XTRP Boards l Clock/control board (1) äfrom CDF clock, generates four phases of 132ns clock äalso generates 33ns clock äcontrols: SYNC, RESET, HOLD äputs all ECL on backplane l Clock/control board transition module äSVT, PreFRED, and L2 I/O through this board l Data board transition module (12) äreceives track data from XFT ädrives info out to Muon,Cal,etc. äall XFT,CAL,MUON I/O through this board

7. Kevin Pitts February 24, 2000 XTRP Review slide - 7 XTRP Data Board l One board per two 15 o wedges ä12 boards total (2 XFT linkers -> 1 XTRP data board) äon board: two wedges denoted “A” and “B” l Functionality älatch XFT data every 33ns ädemux and pipe (FPGA) [also buffer for L1,L2] älookup RAMs ähandle duplicate tracks ädrive data out to CAL and Muon

8. Kevin Pitts February 24, 2000 XTRP Review slide - 8 Recent History

9. Kevin Pitts February 24, 2000 XTRP Review slide - 9 Test Setup (WH 14) l XTRP crate ätest clock äXTRP clock/control board ädata board ädata board transition module l XFT linker crate ä2 XFT linkers äXFT “linker tester” - data blaster/buffer board Clock/control board Data board

10. Kevin Pitts February 24, 2000 XTRP Review slide - 10 Today l Mike Kasten äboard status ätests, test results äplans l Nathan Eddy ätest and readout software package l Hyunsoo Kim ämap generation ädownload software

11. Kevin Pitts February 24, 2000 XTRP Review slide - 11 Schedule

12. Kevin Pitts February 24, 2000 XTRP Review slide - 12 Manpower l Current: äKasten 100%, Eddy 75%, Kim 100% l Future: äKim will play a larger roll in hardware when maps are done äadd at least one grad student soon l Track Trigger: äKasten, Pitts, student ämore UIUC engineering support if needed - Mike Haney largely done with CLEO-III trigger - also get an EE grad student