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Published byLawrence Perkins Modified over 9 years ago
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Op Amp Nonidealities (1) Section 8.4
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Topics DC Offset Input Bias Current Speed Limitations Slew Rate Finite Input and Output Impedance
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DC Offset V io for ST UA741 CN is 1 mV (Typ.) – Cause of offset: mismatch during fabrication
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Symptom of DC Offset Symptom: Vout is not zero when V in2 -V in1 =0 Vos can appear at either input with arbitary polarity.
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Problems Caused by Input Offset Voltage Offset amplified by the gain!
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Saturation Caused by DC Offset Gain=100 Offset of 1 mV What is the gain of this amplifier ? Assume an offset of 1 mV. How much offset appears at X ? 100 mV How much offset is expected at Vout ? Saturation
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Input Bias Current Iio is 10 nA for ST UA741 CN
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Problem Caused by Input Bias Current IB1 has no effect Replace by Thevenin eq. circuit Feedback caused the voltage drop across R2 to be 0
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Input Bias Current Correction Parallel combination of R1 and R2 added in order to cancel offset at the output due to input bias current
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