1. 6 Oct 2003Vince Pavlicek1 Make a BPM out of a Damper?

2. 6 Oct 2003Vince Pavlicek2 53 MHz, TCLK, MDAT,... Digital Damper Monster FPGA(s) Minimal Analog Filter FAST ADC Stripline Pickup Minimal Analog Filter FAST ADC 14 Ethernet 106 / 212 MHz Stripline Kicker Power Amp Minimal Analog Filter FAST ADC Resistive Wall Monitor Broadband Cavity FAST DACs > 27 MHz FAST DACs Power Amp Transverse Dampers Identical X & Y Longi- tudinal (Z) Damper 2-10

3. 6 Oct 2003Vince Pavlicek3 53 MHz, TCLK, MDAT,... Damper -> BPM Analog Filter FAST ADC Stripline Pickup Analog Filter FAST ADC 12 VME 212 MHz BPMs H & V Analog Filter FAST ADC Stripline Pickup Analog Filter FAST ADC 12 Timing Logic FPGA MEMORYMEMORY Delay line per ADC FPGA

4. 6 Oct 2003Vince Pavlicek4 UCD VME CPU + EDB PMC ACNET Clocks and Timing VMEVME FADC – 4 Chan/2 BPM BLM BPM Pick-ups Sample Timing

5. 6 Oct 2003Vince Pavlicek5 Timing and EDB/BLM VME CPU ACNET Clocks and Timing VMEVME FADC – 4 Chan/2 BPM BLM BPM Pick-ups

6. 6 Oct 2003Vince Pavlicek6 So What Do We Get? Minimum: A Sample every bucket, allowing filtering and averaging everything with everything. Multiple data streams. Synchronous sampling and phasing can be beam triggered. Sampling based on the beam structure, i.e the FPGA data rate is proportional to the beam structure. We can time-separate the proton signal from the antiProton signal.

7. 6 Oct 2003Vince Pavlicek7 212MHz Samples Threshold Gate Anti-Gate Bunch Structure Timing Memory Interface Turn Average Bunch n TbyT Filter Bunch m TbyT Filter FPGA Logic example Memory Interface Memory Interface Memory Interface Memory Interface Analog Scope Out-of- bunch Data

8. 6 Oct 2003Vince Pavlicek8 What is the bad news? It isn't a perfect fit to our problem but the core design is close enough that we should be able to use it. It isn't a production board just a good core design we can build upon. It is complete over-kill but it costs $400- $500 per channel today, quantity one.

9. 6 Oct 2003Vince Pavlicek9 What needs to be done? Determine the Analog Filter to use: –Nothing?? –Low Pass Filter only? –Switchable Bandpass Filter to spread the pulse width on uncoalesed bunches? Determine functionality of current board and stuff another one for our testing. Soon, channel # decision. Then layout new board and simulation of VHDL logic.

10. 6 Oct 2003Vince Pavlicek10 Webber Questions are there parallel, simultaneous position processing issues in the new requirements that the FDB architecture can/cannot satisfy? –Nope what are the requirements for switching between modes in a short time? –Run several modes in parallel is the FDB pipeline/FIFO processing architecture limiting in any significant way relative to TeV requirements? –No FIFO, FPGA pipeline runs faster than data rate. are implied VME backplane data rates acceptable? –VME rates are ACNET request dependent. Boards can buffer data. what might be possibility of excessive loading on VME CPU? –Programmer dependent. what are the triggering implications and requirements on external timing/triggering system? –Noticeable, timing must sync to accelerator clock.