1. Malte Backhaus – University of Bonn – ??/??/201?1 Approaching FLEX-test PrimList - Upcoming questions Malte Backhaus

2. Malte Backhaus – University of Bonn – ??/??/201?2 ToT Tuning Module tuning (noise, low threshold, NOcc) more robust with lower feedback current. Performed some tests to check for reasonable feedback current for production test tunings  robust  Am energy resolution  good starting point for IBL operation (pile-up, timewalk, …) Tuned a module to 1500 electrons threshold (to be sensitive to any effect) and 6 ToT @ 16 ke (ToT Code  7 ToT in bx) Injected 16 ke for 51 global feedback current settings to measure ToT response Run threshold scan for these 51 global feedback current settings to check the threshold (noise) Plot threshold (noise) as a function of ToT response for 16 ke

3. Malte Backhaus – University of Bonn – ??/??/201?3 ToT Tuning

4. Malte Backhaus – University of Bonn – ??/??/201?4 ToT Tuning

5. Malte Backhaus – University of Bonn – ??/??/201?5 ToT Tuning Need to define reasonable feedback current value –Results + experience favor low feedback current Summary of ongoing discussion: –Pile-up  high feedback current. FE-I4 designed with assumption of 400ns return to baseline (not ToT) for a mip. That‘s ToT = ~12. –Timewalk  For single LVL1 operation we need negligible timewalk for hits with ToT > 2. More studies needed. –Low threshold operation for good S/N  see results. Favor low feedback current. Consistent with FE-I4 design optimization. –Charge measurement. For Am-source low feedback current needed, for Landau reconstruction higher feedback current optimal. Landau reconstructionn not important for IBL operation (no particle ID with IBL)? Proposal: Tune to 9 ToT @ 16 ke (10 ToT in bx).

6. Malte Backhaus – University of Bonn – ??/??/201?6 Generic ADC (GADC) calibration/test FE-I4B hosts a on-chip ADC. Can measure: 1.Temperature 2.GADC reference voltage 3.AGND 4.Analog MUX output 5.Analog regulator current 6.PulserDAC output (input to pulser circuitry) 7.½ VDDA 8.Ileak Need to calibrate and test GADC on modules (not done on wafers) Idea: Use ½ VDDA to calibrate GADC (analog regulator output scanned on modules to test the LDOs)

7. Malte Backhaus – University of Bonn – ??/??/201?7 Generic ADC (GADC) calibration/test

8. Malte Backhaus – University of Bonn – ??/??/201?8 Generic ADC (GADC) calibration/test

9. Malte Backhaus – University of Bonn – ??/??/201?9 ToT Tuning Module FLEX test primitive list growing. Contains now: –IV-Scan –Reading of FE SN –Register tests –LDO tests –GADC test/calibration –Digital test @ high threshold –Tuning: working robust now (took some time) –Threshold Scan with HV –Threshold Scan without HV –xTalk check with HV –xTalk check without HV –ToT verification after FDAC Tuning –ToT verification after final TDAC tuning Tuning proceedure settles  time to add more std. tests: T0-Scan, Timewalk scan, InTime-Threshold, ToT-Charge calibration?, Pulser Offset scan (needs fixed ration of Chigh/Clow), … More tricky: Min threshold scan

10. Malte Backhaus – University of Bonn – ??/??/201?10