Hasan Arslan and Shantanu Dutt Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago DATE 2006 Efficient Timing-Driven.

Hasan Arslan and Shantanu Dutt Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago DATE 2006 Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Dutt & Arslan, UIC Outline Introduction Introduction Importance of Incremental Routing Importance of Incremental Routing Previous Work Previous Work Our Goals Our Goals A DFS-Based TD Incr Routing Algorithm (TIDE) A DFS-Based TD Incr Routing Algorithm (TIDE) Previous work on global TD routing Previous work on global TD routing Global Routing with slack tolerance concepts Global Routing with slack tolerance concepts Detailed Routing with DFS-based B&R Detailed Routing with DFS-based B&R Experimental Results Experimental Results Conclusion Conclusion

Dutt & Arslan, UIC Incremental Routing After chip layout is completed After chip layout is completed Time/noise/thermal violation Time/noise/thermal violation One or more optimization metrics (speed/power/area) unsatisfactory One or more optimization metrics (speed/power/area) unsatisfactory Need correcting changes to the circuit/system Need correcting changes to the circuit/system Engineering Change Order (ECO) process Engineering Change Order (ECO) process Enormous resources and time already spent Enormous resources and time already spent Time to meet market requirements Time to meet market requirements Most ECOs lead to a requirement of routing changes after various design changes at earlier levels Most ECOs lead to a requirement of routing changes after various design changes at earlier levels The ECO could also be at the routing level The ECO could also be at the routing level Incremental routing & interconnects critical Incremental routing & interconnects critical Need a time-efficient & effective TD-incremental routing algorithm Need a time-efficient & effective TD-incremental routing algorithm

Dutt & Arslan, UIC Incremental Routing Problem Incremental Routing Problem Set of existing routed nets R = E – D, E = original nets before ECO, D = deleted nets Set of existing routed nets R = E – D, E = original nets before ECO, D = deleted nets Set of new nets S (resulting from correcting re- synthesis at different levels of the VLSI design flow) Set of new nets S (resulting from correcting re- synthesis at different levels of the VLSI design flow) Quality metrics Quality metrics Time-efficient near-optimal incr solns for S subject to given constraints (slack satisfaction, crosstalk bounding, etc.) Time-efficient near-optimal incr solns for S subject to given constraints (slack satisfaction, crosstalk bounding, etc.) Minimal changes to previous routing results Minimal changes to previous routing results Complete incr routing in the available metal layers (if such a soln exists) Complete incr routing in the available metal layers (if such a soln exists) Incremental Routing (Cont.)

Dutt & Arslan, UIC Prior Work on Incremental Routing 1) Emmert and Bhatia, “Incremental Routing in FPGA”, IEEE Int. ASIC Conference, 1998. 1) Emmert and Bhatia, “Incremental Routing in FPGA”, IEEE Int. ASIC Conference, 1998. 2) Cong and Sarrafzadeh, “Incremental Physical Design”, ISPD 2000. 2) Cong and Sarrafzadeh, “Incremental Physical Design”, ISPD 2000. 3) Dutt, Shanmugavel and Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”, ICCAD 1999. 3) Dutt, Shanmugavel and Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”, ICCAD 1999. 4) Dutt, Verma and Arslan “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in FPGAs”, TODAES 2002 4) Dutt, Verma and Arslan “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in FPGAs”, TODAES 2002 5) Xiang, Chao, Wong “An ECO Algorithm for Eliminating Crossalk Violations”, ISPD 2004 5) Xiang, Chao, Wong “An ECO Algorithm for Eliminating Crossalk Violations”, ISPD 2004 6) S. Raman, et al., “A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs “, DATE 1996 6) S. Raman, et al., “A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs “, DATE 1996 7) H. Arslan and S. Dutt, “A Depth-First Search Controlled Gridless incremental routing Algorithm for VLSI Circuits”, ICCD 2004. 7) H. Arslan and S. Dutt, “A Depth-First Search Controlled Gridless incremental routing Algorithm for VLSI Circuits”, ICCD 2004. No work on TD incremental routing for ASICs No work on TD incremental routing for ASICs

Dutt & Arslan, UIC Emmert-Bhatia (ASIC’98) Nets connected to faulty PLB, deleted and rerouted Nets connected to faulty PLB, deleted and rerouted Standard single-net routing mode (global then detailed) Standard single-net routing mode (global then detailed) Do not perturb or move existing nets Do not perturb or move existing nets Standard Net Routing : Route new nets without perturbing existing nets Standard Net Routing : Route new nets without perturbing existing nets Rip & Reroute : If some nets cannot be routed, rip-up “blocking” existing nets. Reroute the ripped up nets. Rip & Reroute : If some nets cannot be routed, rip-up “blocking” existing nets. Reroute the ripped up nets. Cong-Sarrafzadeh (ISPD’00) Prior Work (Cont.)

Dutt & Arslan, UIC Our Goals TD-incremental routing for VLSI (ASIC) circuits TD-incremental routing for VLSI (ASIC) circuits Address quality metrics of incr. routing and satisfy constraints Address quality metrics of incr. routing and satisfy constraints Satisfy slack constraints on new and existing nets that may be affected by new net routing Satisfy slack constraints on new and existing nets that may be affected by new net routing Fast near-WL,via-optimal incr solutions Fast near-WL,via-optimal incr solutions Min. changes to existing routing-bounded WL, via increase Min. changes to existing routing-bounded WL, via increase Complete incr routing in the available metal layers—aggressive exploration of routing space within above constraints Complete incr routing in the available metal layers—aggressive exploration of routing space within above constraints

Dutt & Arslan, UIC n 1 n 2 n 3 n 2 Adj-via Adj-via n j Bumped seg. High-Level Approach Global Routing of new net based on: 1) A new iterative slack-satisfaction algorithm IntAl for connecting next pin on the net based on local slack tolerances 2) Congestion + WL + efficiency-based min-cost on a grid-graph for each 2-pin path Detailed routing of new net based on: 1)WL + via + bumping (degree of bumped net) min-cost path for each global route 2) Constraint-satisfying DFS-based partial- B&R process for “overlapped” or “bumped” existing nets so that: a) slacks not violated, b) WL-increment bounded V1 V0V0 VmVm Vj Vi V2V2 V2

Dutt & Arslan, UIC Our Approach – TD Global Routing In an iterative connections of pins on routing tree, most imp. Q: Where to connect the next pin for slack-satisfaction of all pins and min-WL? v0v0 v1v1 v2v2 v3v3 vuvu Simplified rule of thumb: Closer is the connection to CC, more interconnect sharing there is w/ partial tree T & less additional delay seen by other sinks. But more “baggage” (accumulated delay) for new pin v u. Higher up and away from CC the connection is, lesser is the accumulated delay of T seen by v u, but less sharing and more delay seen by other sinks due to more wire-cap load Classic Prim-Dijkstra tradeoffs discussed in [Alpert et al., TCAD’95] Optimal solution (even just slack-satisfying soln. somewhere in between No one has solved it exactly (satisfying all slacks) or optimally (w/ min-WL) We provide a near-min-WL all-slack-satisfying solution here CC (closest connection) vivi New pin

Dutt & Arslan, UIC Various Approaches to TD Global Routing In [Boese, et al., TCAD-95] (SERT/ERT algorithm): – The delay on any sink is a concave function of l x the distance from CC of the connection point – Same for weighted sum of all sink delays (obj. func)—min. @ either v i or CC – Choose v i or CC based on min-WL v0v0 v1v1 v2v2 v3v3 vuvu CC vivi lx vxvx New pin CC vivi delay lx Does not solve the core TD problem of slack satisfaction

Dutt & Arslan, UIC Various Approaches to TD Global Routing (contd) In [Hou & Sapatnekar, ISPD’98] (MVERT): – Constraint satisfaction of all sinks v k is explicitly considered: d(v k ) - slack(v k ) <= 0 (LHS is also concave); uses non-Hanan points – The technique involves navigating max[slack(v k )– d(v k )] via intersection points of the various concave curves – Use binary search to find min-WL point for constr. satisfaction v0v0 v1v1 v2v2 v3v3 vuvu CC vivi lx vxvx New pin CC vivi delay - slack lx 0 vkvk Optimal slack- satisfying conn. point Max envelope Time complex—, where k = # sink pins (our analysis) Misses some slack satisfaction solutions from initial SERT/ERT handoff

Dutt & Arslan, UIC Various Approaches to TD Global Routing (contd) As our competitor, we consider a mix of SERT [Boese, TCAD’95] and SOAR [Wang and Kuh, MCMC’97] (SERT/SOAR): – Check if connection to CC satisfies all slacks – Else make a connection to driver v 0 – Rationale:  If connection to CC violates slack to v u, then this is most likely due to the “baggage” delay of shared interconnects.  This can be avoided maximally by routing directly to v o  Classical Prim-Dijkstra tradeoff  Fast v0v0 v1v1 v2v2 v3v3 vuvu CC vivi lx vxvx New pin

Dutt & Arslan, UIC Our Approach to TD Global Routing Exact slack satisfaction of all sinks in “constant” time by checking satisfaction of derived slacks (called tolerances) as a function of l x of only 3 classes of sinks: – vu– vu – sinks in T(CC), where T(u) is routing subtree rooted at u (e.g., v 3 ) – sinks below T(v i )/T(CC) (e.g., v 1, v 2 ) For this we need tolerance concepts discussed next v0v0 v1v1 v2v2 v3v3 vuvu CC vivi lx vxvx New pin Derived tolerances

Dutt & Arslan, UIC Elmore Delay Model v0v0 vivi vjvj l ij C dn j D(v j ) = D(v i ) + (r.c.l 2 ij )/2 + r.l ij.C dn j C dn j = gate + wiring capacitance of subtree rooted at v j If v j is a sink pin, C dn j = C g (v j ) [gate cap of v j ] r, c = unit wire cap, res Has good fidelity

Dutt & Arslan, UIC Tolerance Concepts—Delay Tolerance

Dutt & Arslan, UIC Tolerance Concepts—Capacitance Tolerances Min = upstream res. from v o To v j

Dutt & Arslan, UIC Intersection ViVi Global Routing: Connecting a New Pin—Interval Intersection (IntAl) Algorithm V2V3V4 VjVj Set 2 CC Vu Δcap x V’ V6 V5 Set 1 V0V0 Set 3 V1 Optimal point h(x) = c.x + l <= 0 g(x)= -r.c.x 2 +ex+m <= 0 Determine valid intervals for each inequality If all intervals are non-empty, take intersection If intersection non-empty – then take bottom point of intersection as min- WL slack-satisfaction point – else prune tree and repeat process with next nearest pruned-tree branch f(x)= -r.c.x 2 +bx+d <= 0 IntAl Algorithm Theorem 1: The tree truncation method in the IntAl algorithm will always find a slack- satisfying connection point for new pin nearest valid edge, if one exists, of the partial routing tree T Updates of tolerances done on an as-needed basis. E.g., change in delay at a sink pin due to re-routing is only propagated to ancestors’ tolerances. Later when a node’s tolerance is needed, it may not be updated but this is accomplished by scanning all its ancestors.  (h) time complexity per rerouting of T, h is T’s height Properties Tol cap (v’) = Tol cap (v j ).R up (v j )/R up (v’) Concave function x delay

Dutt & Arslan, UIC Timing-Driven Incremental Detailed Routing If a portion of net n i is overlapped If a portion of net n i is overlapped Length of overlapped portion might be increased. Length of overlapped portion might be increased. Increase the capacitance. Increase the capacitance. Slack of sink pins might be violated. Slack of sink pins might be violated. Possible overlapping: Possible overlapping: With leaf interconnect With leaf interconnect Interior edge Interior edge Steiner point Steiner point Our goal: Satisfy source to sink delay requirement for all sink pins (slack) Slack: The amount of delay can be added on a net connecting the sink pin without increasing the maximum delay requirement of that sink pin. Detailed routing of new net based on: 1)WL + via + bumping min-cost path for each global route 2) Constraint-satisfying DFS-based partial- B&R process for “overlapped” or “bumped” existing nets so that: a) slacks not violated, b) WL-increment bounded n 1 n 2 n 3 n 2 Adj-via Adj-via n j Bumped seg.

Dutt & Arslan, UIC TD Incr. Detailed Routing—Overlapping a Leaf Interconnect TD Incr. Detailed Routing—Overlapping a Leaf Interconnect Self Test: Self Test: Downstream Test: Downstream Test: Upstream Test Upstream Test n2n2 n2n2 Δcap V6 V5 V1 V2 Vj V4 Vi T V0 n1n1

Dutt & Arslan, UIC TD Incr. Detailed Routing—Overlapping an Interior Interconnect TD Incr. Detailed Routing—Overlapping an Interior Interconnect  D(v’ j ) <= Tol del (v’ j ) = Tol del (v j ) 2)For each child v k (sink pin or Steiner node):  D(v k ) <= Tol del (v k ) [e.g.,  D(v 2 ) <= Tol del (v 2 ),  D(v m ) <= Tol del (v m ) ]  D(v’ j )  D(v 2 )  D(v m ) Do these checks only V2V2 VmVm VjVj n2n2 n2n2 ViVi V’’ j V6V6 T V0V0 n1n1 V3V3 V4V4 V5V5 V’ j Δcap Upstream Test: Upstream Test: Downstream Test: Downstream Test: i

Dutt & Arslan, UIC (a) (b) (c) (a) (b) (c) (b) moving v j upwards will increase capacitance and resistance (c) moving v j downwards decrease cap. change Steiner node V1V2V3V4 Vj Vk n2n2 n2n2 V5 T Vn n1n1 V1V2V3V4 n2n2 n2n2 V5 T Vn n1n1 Δcap V’j V1V2V3V4 Vj V’k n2n2 n2n2 V5 T Vn n1n1 V’j TD Incr. Detailed Routing—Overlapping Steiner Point TD Incr. Detailed Routing—Overlapping Steiner Point Vi

Dutt & Arslan, UIC Constraint Satisfying DFS-Controlled Routing with Partial B&R n1n1 njnj n2n2 n3n3 n 1..b-seg n 3..h 1 n 3..v 1 njnj n 1.b-seg njnj n 2..h 1 P i = i-via path is explored n 2..h 2 n 1..b-seg n 2.pin or obs P1P1 n 1..b-seg n 2..h 2 n 2.h 2 P2P2 DFS retractions: pin or logic as obstacles ancestor nets bumped slack violation of current net WL of currently re-routed net excessive other constraints Exploring a richer solution space via partial bump-&-reroute (B&R) of existing nets Constraint of minimal effect on B&R’ed nets need to be satisfied: slack staisfaction, min-WL Adapted from [Arslan & Dutt, ICCD’04]

Dutt & Arslan, UIC n1n1 njnj n2n2 n3n3 n 3..h 1 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 2..h 2 n 1..b-seg n 2..h 2 DFS-Controlled Routing with Partial B&R

Dutt & Arslan, UIC n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg n 2..h 2 P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 DFS-Controlled Routing with Partial B&R

Dutt & Arslan, UIC n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj n 2..h 1 P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 n 2..h 2 obs P1P1 obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 DFS-Controlled Routing with Partial B&R

Dutt & Arslan, UIC n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 n 1..b-seg P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 obs P1P1 obs or anc.n 1 or anc.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 n 2.h 1 P2P2 n 2..h 1 obs P1P1 n 1..b-seg DFS-Controlled Routing with Partial B&R

Dutt & Arslan, UIC n1n1 njnj n2n2 n3n3 n 3..v 1 njnj n 1.b-seg n 2.pin or obs P1P1 njnj P i = i-via path is explored n 2.h 2 P2P2 n 3.v 1 P1P1 P1P1 obs P1P1 anc obs or anc.n 1 or anc.n j P 2 -P 4 n 3.h 1 P 2 -P 3 obs P1P1 obs or anc.n 1 or an.n j P 2 -P 4 n 3..h 1 n 3..v 1 n 2..h 2 n 2.h 1 P2P2 obs P1P1 VGL P2P2 n 2..h 1 DFS-Controlled Routing with Partial B&R net lenghts and # of vias of all modified/bumped nets unchanged

Dutt & Arslan, UIC Benchmark Circuits Benchmarks: Benchmarks: 10 circuits ranging from 1643 to 10435 nets & 7200 to 47520 pins 10 circuits ranging from 1643 to 10435 nets & 7200 to 47520 pins Base 2x2 tile of Mcc1 bench. is repl. with diff. cell sizes and diff. # of pins Base 2x2 tile of Mcc1 bench. is repl. with diff. cell sizes and diff. # of pins Nets randomly generated & routed using SERT/SOAR Nets randomly generated & routed using SERT/SOAR Net distribution: 2-pin: 30%, 3-4 pins: each 20%, 5 pins: 10%, 6-7 pins: each 5%, 8-10 pins: each 2%, 11-14 pins: each 1% Net distribution: 2-pin: 30%, 3-4 pins: each 20%, 5 pins: 10%, 6-7 pins: each 5%, 8-10 pins: each 2%, 11-14 pins: each 1% Pin slacks normally distributed in range [0,5% max delay on net] Pin slacks normally distributed in range [0,5% max delay on net] Ran on 2.6 Ghz Pentium Linux machines, 1GB RAM Ran on 2.6 Ghz Pentium Linux machines, 1GB RAM Simulation: Randomly deleted 10% nets & rand. gen. 10% new nets Simulation: Randomly deleted 10% nets & rand. gen. 10% new nets Evaluation: Crash Test—routing as many nets as possible under the constraint of only 2 metal layers & slack satisfaction Evaluation: Crash Test—routing as many nets as possible under the constraint of only 2 metal layers & slack satisfaction (TD-S, TD-R, TIDE) (TD-S, TD-R, TIDE) TD-S (TD-R) is SERT/SOAR overlaid on Std (R&R) TD-S (TD-R) is SERT/SOAR overlaid on Std (R&R)

Results 5.6x 4.7x 5.3x 4.2x 9.8x 9.5x 7x 6.7x Times TIDE is better 1) % Unrouted Nets 2) Slack Violations

Dutt & Arslan, UIC Results 3x 6.7x Times TIDE is better 2.6x 4.4x 3) Average Routed Net Length 4) Vias per New Net

Dutt & Arslan, UIC Results 2x 9.5x 0.5x 2.4x 5) Modified Nets per New Net 6) Runtime Times TIDE is better

Dutt & Arslan, UIC Conclusions New TD Incremental Routing Algorithm TIDE New TD Incremental Routing Algorithm TIDE Uses new concepts of derived tolerances @ Steiner nodes to: Uses new concepts of derived tolerances @ Steiner nodes to: a) In global routing—quickly determine slack-satisfying near-min-WL connection of the next pin for a new net routing b) In detailed routing—quickly determine slack satisfaction of B&R’ed nets In global routing, the IntAl algorithm is the first in pruning trees (proven correct) for determining the next nearest connection point after the recent attempt failed. In detailed routing, high-level DFS control  good routing soln. for new nets with min. impact on existing nets In detailed routing, high-level DFS control  good routing soln. for new nets with min. impact on existing nets Produces significant improvement over TD-Std and TD- R&R in all important metrics of interest and is reasonably fast Produces significant improvement over TD-Std and TD- R&R in all important metrics of interest and is reasonably fast Future Work Future Work TD incremental placement and integration with TIDE TD incremental placement and integration with TIDE

Dutt & Arslan, UIC THANK YOU

Hasan Arslan and Shantanu Dutt Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago DATE 2006 Efficient Timing-Driven.

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Hasan Arslan and Shantanu Dutt Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago DATE 2006 Efficient Timing-Driven.

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