1. Interconnect Planning, Synthesis, and Layout for Performance, Signal Reliability and Cost Optimization SRC Task ID: 605.001 PI: Prof. Jason Cong (UCLA) Graduate Students: Chin-Chih Chang, David Pan, Xin Yuan Industrial Liaisons: Dr. Prakash Arunachalam (Intel) Dr. Norman Chang (HP) Dr. Wilm Donath (IBM) Dr. Stefan Rusu (Intel) SRC Monitor: Lawrence Arledge (SRC)

2. Project Overview n Objective: investigate an interconnect-centric design flow and methodology, consisting of: u Interconnect Planning u Interconnect Synthesis u Interconnect Layout

3. Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Final Layout abstraction Structure view Functional view Physical view Timing view HDM Synthesis and Placement under Physical Hierarchy Interconnect Planning Physical Hierarchy Generation Foorplan/Coarse Placement with Interconnect Planning Interconnect Architecture Planning Interconnect Optimization (TRIO) Topology Optimization with Buffer Insertion Wire sizing and spacing Simultaneous Buffer Insertion and Wire Sizing Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Interconnect Performance Estimation Models (IPEM) OWS, SDWS, BISWS Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control

4. Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Final Layout abstraction Structure view Functional view Physical view Timing view HDM Synthesis and Placement under Physical Hierarchy Interconnect Planning Physical Hierarchy Generation Foorplan/Coarse Placement with Interconnect Planning Interconnect Architecture Planning Interconnect Optimization (TRIO) Topology Optimization with Buffer Insertion Wire sizing and spacing Simultaneous Buffer Insertion and Wire Sizing Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Interconnect Performance Estimation Models (IPEM) OWS, SDWS, BISWS Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control Interconnect Layout Route Planning Point-to-Point Gridless Routing Interconnect Performance Estimation Models (IPEM) OWS SDWS BISWS Interconnect Optimization (TRIO) Topology Optimization with Buffer Insertion Wire sizing and spacing Simultaneous Buffer Insertion and Wire Sizing Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Planning Physical Hierarchy Generation Foorplan/Coarse Placement with Interconnect Planning Interconnect Architecture Planning

5. Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Final Layout abstraction Structure view Functional view Physical view Timing view HDM Synthesis and Placement under Physical Hierarchy Interconnect Planning Physical Hierarchy Generation Foorplan/Coarse Placement with Interconnect Planning Interconnect Architecture Planning Interconnect Optimization (TRIO) Topology Optimization with Buffer Insertion Wire sizing and spacing Simultaneous Buffer Insertion and Wire Sizing Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Interconnect Performance Estimation Models (IPEM) OWS, SDWS, BISWS Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control

6. Review: Accomplishments in Year 1& 2 n Efficient (constant time) and accurate (90%) interconnect delay estimation models for 2-pin nets under different interconnect optimization algorithms [Cong-Pan, IWLS’98, SRC/TECHCON’98, ASPDAC’99] n Interconnect architecture planning [Cong-Pan,DAC’99] n Efficient and accurate interconnect estimation models for multiple-pin nets [Cong-Pan, TAU’99] n Buffer block planning for interconnect-driven floorplanning [Cong-Kong-Pan, ICCAD’99]

7. Accomplishments and Ongoing Works in Year 3 n An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] n Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] n Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] n Ongoing studies on physical planning

8. Accomplishments and Ongoing Works in Year 3 n An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] n Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] n Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] n Ongoing studies on physical planning

9. Crosstalk Noise CxCx Victim net Aggressor net

10. Previous Works n Transmission line equations [Sakurai+, TED’93, ASPDAC’98] u Only handle fully coupled bus lines n Devgan’s model [ICCAD’97] u Elegant, Elmore-like formula for peak noise u Over estimation, esp. when aggressor slew is small => could lead to noise even larger than Vdd ! n Charge-sharing based (e.g., [Vittal & Marek-Sodawska, TCAD’97]) u One lumped R, C for victim/aggressor net u Simple noise formulae for peak noise, and noise amplitude-width product u Cannot differ near-source versus near-sink coupling  Need simple yet accurate model that considers more KEY (but not more than necessary) parameters to guide layout optimization !

11. 2-  Crosstalk Noise Model [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] CxCx Victim net Aggressor net Ls Le Cl Cs1 Tr Rd Rs Ce1 Cs2 Ce2 Cl Re Lc

12. 2-  Model C1=Cs1 Rd Rs C2=Cs2+Ce1 CL=Ce2+Cl Re Cs1 Tr Rd Rs Ce1 Cs2 Ce2 Cl Re

13. Closed-Form Solutions n Peak noise n Let t x : RC delay from upstream resistance times coupling cap. t v : Elmore delay of the victim net n Noise width

14. Unified View for Existing Models n Peak noise s As (Vittal+ TCAD’97 model) s As (Devgan ICCAD’97 model) ( 2-  model) s As (Vittal+ TCAD’99 model, Up to 100% larger than Devgan metric for large t r )

15. Extension to Handle General RC Tree n Essentially the same as for 2-pin nets: u t x still the upstream resistance times coupling capacitance u t v still the victim net’s Elmore delay (with branching capacitances) n Computation complexity u Linear time (in terms of number of wire segments in the RC tree) u The same as Devgan or Vittal’s model (anyhow, one has to traverse the entire tree)

16. Experimental Results n 1,000 random nets based on realistic parameters

17. Results for Multiple-Pin Nets n Scatter diagram for peak noise and noise width by 2-  model versus HSpice simulation for 20 randomly generated 4-pin nets

18. Applications of 2-  Model n We have obtained a set of rules for noise reduction using different interconnect optimizations u Driver sizing u Near source versus sink coupling u Shield insertion u Wire sizing and spacing u AW product (noise amplitude width) n Used in Magma’s BlastFusion software -- U.S. Patent Pending

19. Accomplishments and Ongoing Works in Year 3 n An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] n Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] n Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] n Ongoing studies on physical planning

20. Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Final Layout abstraction Structure view Functional view Physical view Timing view HDM Synthesis and Placement under Physical Hierarchy Interconnect Planning Physical Hierarchy Generation Foorplan/Coarse Placement with Interconnect Planning Interconnect Architecture Planning Interconnect Optimization (TRIO) Topology Optimization with Buffer Insertion Wire sizing and spacing Simultaneous Buffer Insertion and Wire Sizing Simultaneous Topology Construction with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Interconnect Performance Estimation Models (IPEM) OWS, SDWS, BISWS Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control

21. Coupling: 4 Coupling: 2 Pseudo Pin Assignment with Crosstalk Noise Control n Pseudo pin: a point where a net crosses a tile boundary n Pseudo pin assignment: bridge between global routing and detailed routing n Our contributions: Pseudo pin assignment algorithm for gridless general area routing with noise control u Control crosstalk noise u Handle obstacle constraints u Align pseudo pins for detailed routing routability u Reduce the total wire length Vias: 6 Vias: 8

22. Why Crosstalk Noise Control in Pseudo Pin Assignment n What can we do in routing to affect crosstalk? u Buffer insertion (if the global router does it) u Wire ordering u Wire spacing n Determine wire ordering and spacing u Global routing? High complexity, hard to consider obstacles u Detailed routing? Flexibility is low u Pseudo pin assignment? Reasonable complexity and high accuracy

23. PPA Algorithm Overview One layer at a time Optimize one row at a time Maximum strip boundary decomposition: Partition boundary to intervals Coarse pseudo pin assignment: Assign pseudo pins to intervals Detailed assignment within each “strip”: Determine pseudo pin locations

24. A Noise Distribution Example – After Detailed Routing n Test case: scaled mcc2, NTRS’97 0.18 um Tech, 0.3 Vdd noise constraints n Pseudo pin assignment with noise control effectively reduce crosstalk noise and meet noise constraints

25. Noise Estimation - Pseudo Pin Assignment vs. After Detailed Routing Noise after DR close to PPA estimation

26. Accomplishments and Ongoing Works in Year 3 n An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] n Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] n Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] n Ongoing studies on physical planning

27. Motivations for Routing Tree Construction under Fixed Buffer Locations n Given buffer blocks planned in early stage, how to do routing and buffer insertion under fixed buffer locations? n Investigate different buffer block planning schemes. An Example of Floorplan with Buffer Block Planning sink hard block or IP buffer block obstacle source

28. Problem Formulation n The routing tree construction under fixed buffer location (RFB) problem: u Given a net N in a routing graph G=(V,E), find a buffered routing tree that spans N with necessary buffer insertions at given buffer nodes. u Objective: maximize the required arrival time of the source. n Use Elmore delay model for interconnect and switch-level RC model for buffers. n Assume buffer sizes are uniform. pin Hard block or IP Buffer block obstacle

29. RMP (Recursively Merging and Pruning) Algorithm n Basic Idea: u A bottom-up tree construction combined with buffer insertion. u Generate a set of subtrees from sinks and then gradually expand and merge them until a complete tree with best performance is produced. n Key differences from previous approaches u The sets of subtrees may not be disjoint u Multiple subtrees may be generated at a node u Works on a routing graph u Handle multiple-pin nets with fixed buffer locations constraints.

30. Comparison Between RMP and Modified BA-tree Algorithm n Modify BA-tree algorithm [TRIO] to handle fixed buffer insertion (MBA-tree) n Similar to the semi-automatic approach used in real design: “round” ideal buffers in BA-tree to the given buffers in MBA-tree. #pins RMP MBA-tree (adjacent NR) MBA-tree (t-adjacent NR) ratwlratwlratwl 41.0 1.620.901.291.08 51.0 1.990.901.461.13 61.0 1.840.851.290.97 Experimental results of RMP vs. BMA-tree (all data are normalized with respect to RMP). RMP can outperform MBA-tree by up to 50% in terms of delay with comparable wirelength.

31. Accomplishments and Ongoing Works in Year 3 n An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] n Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] n Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] n Further study on physical planning

32. Ongoing Studies on Physical Planning n Motivation u Logical hierarchy is different to physical hierarchy u Planning based on logical hierarchy is limited by floorplanning on logical hierarchy u Planning based on physical hierarchy with performance driven geometric embedded partitioning shows good promises [Cong-Lim ICCAD’00] u Further study on interconnect planning in physical hierarchy

33. Example of Logic Hierarchy in Final Layout By courtesy of IBM (Tony Drumm)

34. Example of Logic Hierarchy in Final Layout By courtesy of IBM (Tony Drumm)

35. Several Ongoing Efforts n Studies on the impacts of layer assignment n Studies on the congestion of global interconnect n A reasonable formulation for physical planning

36. Impacts of Layer Assignments on Delays n Delays estimated by IPEM for optimal buffer insertion and wire sizing n 0.13 um NTRS’97 technology n Delay reduction of changing wires from layers 1-2 to layers 7-8: u 0.5mm: 2% u 6.5mm: 40% u 27.5mm: 49% n The longer the wire, the more possible reduction by assigning to upper metals

37. Several Ongoing Efforts n Studies on the impacts of layer assignment n Studies on the congestion of global interconnect n A reasonable formulation for physical planning

38. Congestion Analysis – Efforts and Preliminary Results n Upper metal layers are used for long wires for reducing delays n Are there enough routing resource on upper metal layers? What is the trend? u How many long wires that need to be routed on upper metal layers? u How much space available on upper metal layers (Power and Clock nets are also competing)? n List of industrial contacts that we consulted: u IBM – Tony Drumm, John Darringer u Intel – Desmond Kirkpatrick, Mosur Mohan, Kris Konigsfeld u HP – Norman Chang

39. Layer Competition under Different Target Delays (Test case from IBM)

40. Several Ongoing Efforts n Studies on the impacts of layer assignment n Studies on the congestion of global interconnect n A reasonable formulation for physical planning

41. Problem Formulation for Physical Planning n Plan the following to achieve optimization goals: u Physical hierarchy with rough geometric information for identifying global interconnects u Retiming and pipelining u Layer assignment for global interconnects u Global net topology generation and congestion control u Buffer planning u … n Estimate and Optimize the following objectives: u Delay u Area u Power u Signal integrity

42. Deliverables n Development of efficient and accurate interconnect performance estimation models for interconnect-driven synthesis and planning (Completed - 30-Jun-1999) n Development of interconnect architecture planning framework (Completed - 30-Jun-1999) n Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the physical level (Completed - 30-Sep-1999) n Development & validation of accurate noise models to guide the interconnect synthesis algorithm for signal reliability (Completed - 31-Dec-1999) n Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets for performance & signal reliability optimization (Completed - 31- Dec-1999) n Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the RTL-level; Software (Planned - 31-Dec-2000)

43. Technology Transfer n TRIO (Tree-Repeater-Interconnect-Optimization) package u Integrated into Intel design technology u http://cadlab.cs.ucla.edu/~trio n IPEM (Interconnect Performance Estimation Model) package u Integrated into IBM design technology u http://cadlab.cs.ucla.edu/software_release/ipem/htdocs n Wire width planning u U.S. Patent pending under SRC sponsorship n BBP (Buffer Block Planning) for physical level floorplanning u Source code transferred to IBM u Interests from Intel and HP n Crosstalk noise modeling u U.S. Patent pending (joint with Magma)

44. Summary n An improved crosstalk model with application to noise constrained interconnect optimization. n Pseudo pin assignment with crosstalk noise control n Routing tree construction under fixed buffer locations n Ongoing studies on physical planning

45. Milestones n Development of a computational model for interconnect architecture planning based on a given design characterization (specified in terms of target clock rate, interconnect distribution, depths of logic,network, etc.) (31-Dec-1998) n Development of estimation models for interconnect layout optimizations suitable for pre-layout synthesis and planning (31-Dec-1998) n Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RTL-level (31-Dec-1999) n Completion of the ongoing effort on the development on a multi-layer general-area gridless routing system (31-Dec-1999) n Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets for performance and signal reliability optimization (31-Dec-1999) n Development and validation of very efficient but accurate noise models to relate the noise with the physical parameters to guide the interconnect synthesis algorithm for signal reliability optimization (31-Dec-1999) n Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the physical level (31-Dec-1999) n Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RT-level (31-Dec-2000)