1. CHAPTER 8 Developing Hard Macros The topics are: Overview Hard macro design issues Hard macro design process Physical design for hard macros Block integration Productization Model development for hard macros Portable hard macros

2. 8.1 Overview The macro developer delivers GDSII and a full set of models to the silicon vendor. The silicon vendor does the physical design for the chip, including integration of the hard macro. The silicon vendor provides the timing and functional models to the chip designer. The chip designer uses the timing and functional models for the hard macro while designing the rest of the chip.

3. 8.1.1 Why and When to use Hard Macros The design is pushing performance to the limit of the silicon process. The design requires some full custom design, and so cannot be delivered in soft form. The value of the macro is so great that the macro provider does not want the chip designers to have access to the RTL. The macro provider wishes to prevent the possibility of the user modifying the macro.

4. 8.1.2 Design Process for Hard vs. Soft Macros The extra steps for hard macros are primarily: Generating a physical design. Developing models for simulation, layout, and timing. Hard macro development is essentially an extension to soft macro development. The design process itself be kept identical with the design process for soft macros except for the productization phase.

5. 8.2 Design Issues for Hard Macros Full Custom Design Interface Design Design for Test Clock and Reset Aspect Ratio Porosity Pin Placement Power Distribution

6. 8.2.1 Full Custom Design Unlike soft macros, hard macros offer the opportunity to include some full custom design in a reusable form. Memory is the first and most natural candidate for full custom implementation. Full custom macros, or full custom components within macros,need to be ported by physical design tools or by repeating the manual design, place, and route.

7. 8.2.2 Interface Design Good interface design is critical to producing high quality, easy to integrate hard macros. Registering inputs and outputs can also eliminate some difficult problems in IP security, manufacturing test, and timing modeling. We recommend erring on the side of too strong a drive strength rather than too weak. Using too strong a drive strength wastes power and area. Using too small a drive strength can result in unacceptable delays.

8. 8.2.3 Design For Test Hard macros do not provide this flexibility; test structures must be built into each hard macro. The hard macro developer must choose between full scan, logic BIST, or application of parallel vectors through boundary scan or muxing out to the pins of the chip. Full scan offers very high test coverage. Scan is the preferred test methodology for hard macros as long as the delay and area penalties are acceptable.

9. 8.2.3 Design For Test (cont) Logic BIST is a variation on the full scan approach. Logic BIST has the advantage of keeping all pattern generation and checking within the macro. Parallel vectors are used to test only the most timing or area critical designs. A robust set of parallel vectors is extremely time-consuming to develop and verify.

10. 8.2.3 Design For Test (cont) Note that for the hard macro test to be fully self-contained, the inputs and the outputs of the macro must be registered. Full custom macros, or full custom components within macros, need to be provide inputs to the hard macro.

11. 8.2.4 Clock and Reset The designer should provide full clock and reset buffering in the hard macro, and provide a minimal load on the clock and reset inputs to the macro. The problem is that the hard macro will have a clock tree insertion delay. This delay affects the setup and hold times at the macro ’ s inputs and its clock-to-output delays. This approach allows a complete clock cycle for the insertion delay, flop delay, and wire delay.

12. 8.2.5 Aspect Ratio The aspect ratio of the hard macro affects the floorplan and routability of the final chip. An aspect ratio close to 1:1 minimizes the burden on the integrator. Aspect ratios of 1:2 and 1:4 are also commonly used. A non-square aspect ratio means that there will be more routing in vertical direction than in the horizontal.

13. 8.2.6 Porosity Designers of leading edge microprocessors, where each block is treated as a hard macro, leave routing channels between blocks and always route around rather than through blocks. The macro deliverables must include a blockage map to identify areas where over- cell routing will not cause timing problems.

14. 8.2.7 Pin Placement Pin placement of the macro can have a significant effect on the floorplan and top- level routing of the chips that use it. A floorplanning model is one of the deliverables of a hard macro. Among other things, this model describes the pin placement, size, and grid.

15. 8.2.8 Power Distribution Power and ground busing within the macro must be designed to handle the peak current requirements of the macro at maximum frequency. The integrator using the macro must provide sufficient power busing to the macro to limit voltage drop, noise, and simultaneous output switching noise to acceptable levels.

16. 8.3 The Hard Macro Design Process We expand the macro specification to include physical design issues. The target library is specified, and timing, area, and power goals are described. Once the macro is partitioned into subblocks, the design of the individual subblocks follows the same process as for soft macros. Note that even with manual synthesis and handcrafting, the RTL for the subblock is the “ golden ” reference. For all synthesis methods, automated and manual, formal verification should be used to ensure the equivalence between the final physical design and the RTL.