1. EMC Design of PCBs

2. Contents Introduction Component selection and mounting PCB trace impedance PCB layer stackup Crosstalk control Power distribution Decoupling

3. Contents Zoning Grounding VIAs connection Termination

4. Introduction

6. EMC Control Measures can be incorporated at three levels. –Primary level (PCB, Circuit etc) –Secondary level (Cables, connector etc) –Tertiary level (Shielding)

7. Introduction

8. Primary Level –Circuit design measures, Board layout grounding Secondary Level –Cables & Connectors Tertiary Level – Apertures,Gaskets etc

9. Component Selection & Mounting Digital circuits –Digital circuits are generator of EMI,high frequency square-waves are rich in harmonics are distributed throughout the system. Analog circuits –Analog circuits are much quieter because high frequency square waves are not normally the feature.

10. Component Selection & Mounting Fourier transform –Basic to understanding of why switching circuit cause interference is the concept of time domain /frequency domain transform –Switching waveform can be represented as trapezoidal with defined rise and fall time.The harmonic amplitude content of a trapezoid decreases from the fundamental at a rate of 20dB per decade until a breakpoint is reached at 1/ptr, after which it decreases at 40dB/decade

11. Component Selection & Mounting

12. It is advisable to use the slowest logic family that will do the job; don’t use fast logic when it is unnecessary. Treat with caution any proposal to substitute devices from a faster logic family, such as replacing 74HC parts with 74AC.

13. Component Selection & Mounting Harmonics contents of different logic families

14. Component Selection & Mounting Some IC manufacturers are addressing the problem of RF emissions at the chip level. By careful attention to the internal switching regime of VLSI devices, noise currents appearing at the pins can be minimized. The transition times can be optimized rather than minimized for a given application. Revised package design and smaller packages can allow the decoupling capacitor to be placed as close as possible to the chip, without the internal lead frame’s inductance negating its effect;

15. Component Selection & Mounting From the point of view of immunity, a slow logic family will respond less readily to fast transient interference

16. Component Selection & Mounting The high frequency spectral content of the component signal are gauged by the signal speed : where f0 is the fundamental frequency (inverse of repetition rate) of its signal, I0 is the magnitude of its drive current, and tr is its rise/falltime

17. Component Selection & Mounting In a digital system we know that the key component of a signal that dictates its high- frequency spectral content is its rise/falltime. In fact we can say that a digital signal has a “bandwidth” that is essentially the reciprocal of its risetime, BW ¼ 1/tr. Hence a clock having a 500 ps rise/ falltime has significant spectral content up to 2 GHz.

18. Component Selection & Mounting In the initial layout of the PCB, a spreadsheet should be compiled of every part to be placed on the PCB according to its “speed”. This priority list should be given to the layout personnel with instructions to apply the greatest care to placement of the highest-speed components at the top of the list and to place the components first according to the highest speed and next to the next lowest speed, and so on.

19. Component Selection & Mounting Numerous automated layout software provide for “autorouting” so that the schematic is laid out and parts connected in a rather automatic manner. This can and usually does create severe EMC problems unless it is used judiciously. It is best to place the highest-speed components manually and to manually route their connection lands with the previous concepts kept in mind

20. Component Selection & Mounting As a general principle, recall that the higher the spectral content of a signal, the greater the ability of that signal to couple inadvertently to other conductors and parts. Hence the highest speed components and the lands they connect should be positioned on the PCB well away from off board connectors and lands as shown below.

21. Component Selection & Mounting

22. Anticipating that the rise/ falltimes of this clock may need to be increased to reduce its high-frequency content, pads should be placed so that (a) a series resistor can be inserted in the lands and (b) a capacitor can be inserted across the lands forming a lowpass filter.

23. Component Selection & Mounting In the beginning, the capacitor pads would not be populated, and a 0-V surface-mount resistor could be placed in series with the clock lands. Later in the design, if problems are uncovered necessitating increasing the clock rise/falltimes, then the capacitor can be added and the value of the series resistor can be changed. Why is this significant? The answer is that no time-consuming repeated PCB layout would be required; only the bill of materials (parts list) need be changed. This is a virtually cost-free solution.

24. Component Selection & Mounting Once again, it is a good practice to place all the components, or at least the higher-speed ones, by hand and not allow automatic software to do this. Perhaps in the future EMC layout rules will be incorporated into these layout tools, but today it seems better to place these components by hand.

25. Component Selection & Mounting Illustration of the unintentional coupling of signals between chip bonding wires, causing supposedly quiet module pins to have high- frequency spectral content. A processor pin, the reset pin, was thought to be “quiet” and hence was connected to a long PCB land. Unsuspected coupling caused it to carry the clock signal, thereby creating large radiated emissions. A series inductor was added to prevent this from occurring.

26. PCB Trace Impedance Track impedance is dominated by inductance at frequencies higher than a few kHz

27. PCB Trace Impedance Where L is the inductance and di/dt is the rate of change of current. For example, consider the case where the power-supply wiring has an inductance of 50 nH. If the transient current, when a logic gate switches, is 50 mA and thegate switches in 1 ns, the noise voltage generated across the power-supply wiring when this one gate changes state will be 2.5 V

28. PCB Trace Impedance Trace inductance of a connection can be reduced in two ways: –minimizing the length of the conductor, and if possible increasing its width –running its return path parallel and close to it. The inductance of a PCB track is primarily a function of its length, and only secondarily a function of its width. For a single conductor of diameter d and length l inches, following equation gives the self-inductance

29. PCB Trace Impedance

30. Two conductors with current in opposite directions (e.g., a signal and its ground return trace) have a total loop inductance Lt, equal to where L1 and L2 are the partial self-inductances of the individual conductors and M is the partial mutual-inductance between them. I To minimize the total loop inductance, the partial mutual- inductance between the conductors should be maximized. Therefore, the two conductors should be placed as close together as possible

31. PCB Trace Impedance Another method for decreasing the inductance of a circuit is to provide alternative paths for current flow. These paths must be electrically, but not necessarily physically, parallel. If two equal inductances are paralleled, then the equivalent inductance will be one half that of one inductor. On many low-cost products, inner plane boards cannot be afforded. Hence the important effects of having a ground plane (and a power plane that can act like a ground plane in returning currents) are not present

32. PCB Trace Impedance On low-cost products where ground plane cannot be afforded, a simple way of reducing the inductance of grounding system is with a gridded ground system.

33. PCB Trace Impedance The limiting case of a gridded ground is when an infinite number of parallel paths are provided and the ground conductor is continuous, and it is then known as a ground plane The main EMC purpose of a ground plane is to provide a low- impedance ground and power return path to minimize induced ground noise

34. PCB layer stackup PCB layer stackup (the ordering of the layers and the layer spacing) is an important factor in determining the EMC performance of a product The following four factors are important with respect to board stackup: –The number of layers –The number and types of planes (power and/or ground) –The ordering or sequence of the layers –The spacing between the layers

35. PCB layer stackup In deciding on the number of layers, the following should be considered: –The number of signals to be routed and PCB cost. –Clock frequency. –Will the product have to meet Class A or Class B emission requirements? –Will the PCB be in a shielded or unshielded enclosure? –The EMC engineering expertise of the design team.

36. PCB layer stackup One- and Two-Layer Boards: –The main EMC concern here is to keep loop areas as small as possible. –One- or two-layer boards should only be considered when clock frequencies are less than 10 MHz –On one- or two-layer boards all critical signals should be routed first, in order to guarantee optimum routing. Critical signals should be routed as short as possible, with an adjacent ground return trace –On two-layer digital boards, the ground and power should be routed so as toform a grid (see Section 10.5.3). It is not unusual to see a 10- to 12-dB decrease in emissions when a ground grid is added to a two-layer digital board that previously did not have one

37. PCB layer stackup Multilayer Boards: –Multilayer boards (four or more layers) using ground and/or power planes provide significant reduction in radiated emissions over two-layer –A often–used rule of thumb is that a four-layer board will produce 20 dB or more, less radiation than a two-layer board—all other factors being equal –Boards containing planes are much better than those without planes for the following reasons: –The planes allow signals to be routed in a microstrip (or stripline) configuration. These configurations are controlled impedance transmission lines that produce much less radiation than the random traces used on one- and two-layer boards

38. PCB layer stackup Multilayer Boards: –When the return current is on the adjacent plane, the loop area is reduced. –The ground plane significantly decreases the ground impedance and hence the ground noise

39. PCB layer stackup Multilayer Boards Objective : –A signal layer should always be adjacent to a plane. –Signal layers should be tightly coupled (close) to their adjacent planes. –Power and ground planes should be closely coupled together.* –High-speed signals should be routed on buried layers located between planes. The planes can then act as shields and contain the radiation from the high-speed traces. –Multiple-ground planes are very advantageous, because they will lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. –When critical signals are routed on more than one layer, they should be confined to two layers adjacent to the same plane. As discussed, this objective has usually been ignored.

40. PCB layer stackup Four layer Board :  A common four-layer board configuration, consisting of two signal layers and two planes, is shown in Fig.  It consists of four uniformly spaced layers with internal power and ground planes. The two external trace layers usually have orthogonal routed

41. PCB layer stackup Four layer Board : If the power plane shown in Figs. 16-12 or 16-13 is split to accommodate different dc voltages, it is important to restrict routing on the bottom signal layer so that traces do not cross the split in the plane. If some traces must cross the split, stitching capacitors should be located close to where the traces cross the split to provide a lower impedance return current path.

42. PCB layer stackup Six layer Board : Most six-layer boards consist of four signal routing layers and two planes. From an EMC perspective, a six-layer board is preferred over a four- layer board because it is easy to shield high-frequency signals by placing them on buried layers between planes, or to provide for orthogonally routed signal layers that are referenced to the same plane.

43. PCB layer stackup Six layer Board :

44. PCB layer stackup Six layer Board :

45. PCB layer stackup Eight layer Board : Most eight-layer board stackups are used to improve EMC performance rather than add additional routing layers. Most eight-layer boards (and all the ones that we will concentrate on here) consist of four signal-routing layers and four planes.

46. PCB layer stackup Eight layer Board :

47. Crosstalk control Crosstalk is one of the several important PCB design that must be considered during any design cycle. Crosstalk refers to the unintended electromagnetic coupling between traces, wires to traces, cable assemblies. Crosstalk between cables, wires and traces affects intrasystem performance. Crosstalk is generally considered to be functionality concern (signal quality)

48. Crosstalk control To cope with this problem, it is essential to have suitable circuit models to simulate complicated structures. Simplified but accurate models are of great help in understanding the crosstalk mechanism. Lumped model of two coupled lines that can be easily implemented in SPICE-like circuit simulators. By virtue of its simplicity, this is the first approach for inexperienced users when dealing with crosstalk and using a commercial circuit simulator that usually does not offer efficient coupled line models in its library.

49. Crosstalk control

53. Near end and Far end Crosstalk Near-End Crosstalk (NEXT), defined as the voltage VNE at point D of the victim line near to the source; Far-End Crosstalk (FEXT), defined as the voltage VFE at point E of the victim line far from the source.

54. Crosstalk control Since the overall coupling effect is the sum of capacitive and inductive crosstalk, near-end crosstalk is of greater magnitude, and hence, of greater concern for a PCB designer.

55. Crosstalk control Techniques to Reduce Crosstalk 1. Use wide traces. 2. Locate traces near to the reference plane. 3. Increase the spacing between traces. 4. Match the lines. 5. Reduce the coupling length. 6. Provide other traces for shielding. 7. Avoid locating critical traces near to the edge of the PCB. 8. Ensure a solid ground plane without cuts.

56. Power Distribution & Decoupling The characteristics of an ideal direct current (dc) power distribution system are as follows: To supply a constant dc voltage to the load Not to propagate any ac noise generated by the load To have a 0 O ac impedance between power and ground

57. Power Distribution & Decoupling There are two primary purposes for using decoupling between power and ground-reference planes. 1.Functionality:

58. Power Distribution & Decoupling Role of decoupling capacitor:

59. Power Distribution & Decoupling Effective power supply decoupling has become increasingly more difficult to achieve as the result of increasing clock frequencies and faster rise times. Ineffective decoupling can lead to excessive power bus noise as well as to excessive radiated emission. It is important to understand that decoupling is not the process of placing a capacitor adjacent to an IC to supply the transient switching current rather it is the process of placing an L–C network adjacent to an IC to supply the transient switching current.

60. Power Distribution & Decoupling 2. To reduce the noise injected into the power and ground reference plane

61. Power Distribution & Decoupling All decoupling capacitors have inductance in series with them. Therefore, the decoupling network is a series resonant circuit. The –inductance comes from three sources, as follows: –The capacitor itself –The interconnecting PCB traces and vias –The lead frame inside the IC

62. Power Distribution & Decoupling The internal inductance of a surface mount technology (SMT) capacitor itself is typically 1–2 nH, the interconnecting PCB traces and vias add 5 to 20 nH or more according to the layout, and the internal lead frame of the IC may have 3 to 15 nH of inductance according to the type of IC package. The inductances of the interconnecting PCB traces, however, are usually the only parameters under the system designer’s control. From the above, we observe that the total inductance can vary from a low of about 10 nH to a high of 40 nH. Typically it is in the range of 15 to 30 nH. It is this inductance that limits the effectiveness of the decoupling network. It is very important to remember this fact—we are placing an L–C network between the power and ground, not a capacitor