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“Supporting the Total Product Life Cycle”

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Presentation on theme: "“Supporting the Total Product Life Cycle”"— Presentation transcript:

1 “Supporting the Total Product Life Cycle”
XC9500 CPLDs “Supporting the Total Product Life Cycle” Technical seminar

2 Designer's Needs In-System Programming Enhanced Testability
Design changes without PCB changes Mixed 5V/3.3V I/Os High endurance reprogramming Multiple speeds/densities in identical pinouts and packages This is a partial list and varies among the many designers using CPLDs today. The most frequently requested feature is ISP, to eliminate sockets and programmer dependence. Additional testability is very desirable, assuring the best quality is delivered to customers. Prototyping without having to rework PCBs is clearly an advantage. The ability to combine both 5V and 3.3V I/Os through a simple interfacing chip is also very important. High endurance reprogramming may not actually be critical, because most people can get their prototypes working in less than 100 retries, but by having thousands of retries new applications and markets will be available. Finally, supplying several speed grades and densities in identically pinned packages permits designers to have multiple dimensions to which they can drive their designs. Technical seminar

3 The Industry’s First 5V Flash CPLD
5 V In-System Programming (ISP) High performance 5ns pin-to-pin speed 125 MHz count frequency Large density range 36 to 288 macrocells (Phase 1 family) Flexible architecture optimized for pin-locking global and product term clock, set/reset, OE Most complete IEEE (JTAG) Highest reprogramming endurance 10,000 program/erase cycles Clearly, the XC9500 is the first family providing 5V Flash based CPLD capability. Others have delivered 5V E EPROM and some have supplied 12V Flash, but Xilinx is the first to deliver 5V Flash. Current speeds are to 5 nsec with 125 MHz, and the first phase family spans from 36 to 288 macrocells, but more important is that this family was architected specifically to address the special needs of In System Programming. Specifically, both the architecture and design S/W were developed to optimize pin locked design styles. As well, the JTAG interface delivered by XC9500 parts is substantially more complete than any other CPLD manufacturer's. And finally, the Fast FLASH technology delivers over 10,000 program/erase cycles. Technical seminar

4 Smaller Cell Size with FastFLASH
Typical E2 CPLD Cell FastFLASH Cell 1/3 Area Product benefits due to smaller cell More routing switches in the same area supports pinlocking Lower parasitic capacitance improves performance Long term cost improvements due to scalability Technical seminar

5 XC9500 Architectural Features
Predictable, all pins fast, PAL-like architecture FastCONNECT switch matrix provides 100% routing with 100% device utilization Flexible function block 36 inputs with 18 outputs product term expansion with up to 90 product terms per macrocell global and product term clocks global and product term 3-state enables global and product term set/reset signals Technical seminar

6 Programming Controller I/O - Global Tri-States
XC9500 Architecture 3 JTAG Controller In-System Programming Controller JTAG Port Function Block 1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O I/O - Global Clocks Function Block 3 3 I/O - Global Set/Reset 1 Function Block n I/O - Global Tri-States 2 or 4 Technical seminar

7 FastFLASH Function Block
Global Clocks 3 Global 3-State 2 I/O Macrocell 1 Product- Term Allocator AND Array 36 From FastCONNECT Macrocell 18 I/O To FastCONNECT Technical seminar

8 to/from other macrocells to/from other macrocells
XC9500 Macrocell to/from other macrocells From FastCONNECT SUM-Term Logic 36 XOR Register 18 P-Term Allocator D/T Q P-term Clk R S P-term R&S P-term OE to/from other macrocells 3 2 or 4 Global Clocks Global R/S Global OEs Technical seminar

9 XC9500 Advanced Macrocell From Upper Macrocell To Upper Macrocell Global S/R Global CLKs Zooming into a Function Block, we see an array of 18 macrocells. Functionally and positionally, all macrocells are identical. There are no “block edge” effects, because the macrocells are arranged in an electrical circile where each macrocell has exactly two nearest neighbors - the upper neighbor and the lower neighbor. This relationship eliminates any functional bias that may exist when resources need to be shared among the macrocells. Examining the macrocell above, we see 5 basic product terms that can connect in a number of ways to the flip flop, or bypass it if needed. Each product term has three options. First, each one has a macrocell specific specialty function - like product term clock, product term set or reset, product term tri-state or drive one input tothe EX-OR gate. The EX-OR gate is available to form parity, adders and so forth, and is not used to configure the flip flop as a T flop. A second use for the procut terms is to form a logical sum of products for the local flip flop. The final use for a product term is to be made available to forward to the upper or lower neighbor. Each product term is configured in one of three ways at the macrocell site, and they are all independent. When a product term is forwarded to the upper or lower neighbor, it incurs 0.75 nsec additional time delay for the fastest parts. The next foils will show how product terms are delivered to neighboring macrocells. Global S/R Product Term OE From Lower Macrocell To Lower Macrocell Technical seminar

10 Flexible Cascading Fast Bi-directional cascade
Forwards 3 p-terms, retains 2 p-terms Fast Bi-directional cascade collects/delivers available p-terms Automatically controlled by software One p-term granularity level Forwards 5 p-terms Macrocell Logic with 18 p-terms Delivers 5 p-terms This diagram focuses on providing product terms to neighboring cells. Additional details - like the flip flops and various muxes are omitted. In this case, we wish to provide 18 product terms to one macrocell output within the function block. First, five product terms are available right at that macrocell site. Next, the design software steers the five from below to the north, taking the tally to 10 product terms. In parallel with this, the software steers the five product from the upper neighbor down, taking the tally to 15 product terms. At this point, we need another 3 product terms, which happen to be available at the upper macrocell which is two away from our destination. Here, two are required to remain to satisfy the needs at that site, but the available three are passed over one macrocell to finally visit our destination. This is one way in which to satisfy the 18 p-term need. The total time is two cascade delays. This is because the immediately adjacent delays both occur in parallel, and the furthest time delay is one additional cascade. For a 5 nanosecond part, this will deliver 18 product terms to the target site in 6.5 nanoseconds. Designers can control this be simply dictating their time constraints and letting the software automatically manage the cascading structure. Delivers 5 p-terms Technical seminar

11 Feedback Paths FastCONNECT Pin Local FastCONNECT FB X Macrocell
Local feedback FastCONNECT feedback Pin feedback Technical seminar

12 Complete Interconnectivity with FastCONNECT™
Global S/R Global 3-State Function Block Function Block Function Block FastCONNECT Function Block Function Block Function Block Function Block Function Block JTAG Global Clocks Technical seminar

13 Restrictive Max7000/S Interconnect
1 2 3 4 36 Pin Inputs (~ 2 entries / LAB) Macrocells (~2 entries / LAB) Technical seminar

14 XC9500 FastCONNECT Pin Inputs Macrocells 1 2 3 4 36 (~ 3 entries / FB)
Technical seminar

15 What is Pin-Locking? Ability to retain device pin assignments for small to medium design changes introducing a new variable to existing terms adding input signals inverting signals introducing 1or 2 buried flip flops adding p-terms Requires a symmetric, uniform architecture Requires software focus on pin-locking PAL designers expect to pinlock, and many designers are frustrated when they cannot retain their pinouts. The list shown are the most commonly expected edits to be able to make, but many CPLD architectures can't do these edits unless they are extremely under utilized. Typically, these are at 50% and below. Designers that frequently expect 90% or more utilization encounter pinlocking problems frequently. The real solution combines both architecture features as well as a S/W pinlocking strategy. Technical seminar

16 Pin-Locking is Key for ISP
Must retain pinouts as the design evolves best done when the design software initially assigns pins different from pinout pre-assigning strong function of utilization in typical CPLD architectures result of both architecture and software strategy Pin-locking is valuable eliminates or reduces PC Board rework minimizes time to market, saves money lowers designer frustration, risk Pinlocking is Key for ISP. This is because designers are literally doing their development right on the PCB. Pinouts must be kept, or the advantage is lost. With other architectures, there is a much stronger relationship to the utilization of the device and its ability to retain pinouts. Clearly, S/W is a key factor. Clearly, the architecture must be designed for this. Pinlocking is valuable. Technical seminar

17 Leading Edge Features Support Superior Pin Locking for ISP
3X more routing switches - superior input/feedback routability FastCONNECT Function Block 36 I/O Block Wired-AND Capability Largest block fan-in - 36 direct inputs - wired-AND provides extra logic/more fan-in Key to XC9500 product advantage is Pin-Locking. With both ICs and software designed from the ground up for pin-locking, the XC9500 has a unique advantage compared to ALL other CPLD competitors. Highlighted above are the main reasons why the XC9500 architecture is so good at pin-locking. These are all unique features which the competitors do not have, especially Altera. ISP without excellent pin-locking is like a feature without a benefit. And with ISP applications growing, customers will NEED the best pin-locking available, and that only comes from the XC9500. Powerful bi-directional logic allocation - any number of p-terms (up to 90 max.) Technical seminar

18 XC9500 Supports Design Changes with Fixed Pinouts
Design Change XC9500 Feature Add another input FastCONNECT switch matrix pin or FB output with 100% connectivity Add more logic in XC9500 allows expansion the macrocell up to 90 P-terms Add additional input 36 total inputs are available connections to the FB plus FastCONNECT AND gate capability Technical seminar

19 XC9500 System Features Enhanced Data Security Features
Read security bits prevent unauthorized reading Write security bits prevent accidental program/erase Reduced power option per macrocell 3.3v/5v outputs 24 mA, 100% PCI compliant Output Noise Reduction Slew rate control User programmable ground pin capability Additional Ground Pin Lower ground inductance Reduce ground noise Internal Logic User Programmable Ground Pin User I/O Pin User I/O Pin Ground Pin Technical seminar

20 Advanced System Features
Enhanced Data Security Features Read security bit prevents unauthorized reading Write security bit prevents inadvertent user program/erase System Power Reduction Reduced power option per macrocell Output drive capability 3.3v/5v outputs 24 mA, 100% PCI compliant outputs Output Noise Reduction in High-Pincount PQFP Packages Slew rate control User programmable ground pins Technical seminar

21 Planned FastFLASH™ CPLD Family
0.6µ Phase I Family Phase II Expansion XC9536 XC9572 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576 Macrocells 36 72 108 144 180 216 288 432 576 Usable Gates 800 1600 2400 3200 4000 4800 6400 9600 12800 tPD (ns) 5 7.5 7.5 7.5 10 10 10 12 15 Registers 36 72 108 144 180 216 288 432 576 Max. User I/Os 34 72 108 133 168 168 192 240 240 Packages 44PC 44PQ 84PC 100PQ 84PC 100PQ 160PQ 100PQ 160PQ 160PQ 208PQ 160PQ 208PQ 208PQ 304PQ 304PQ 304PQ Technical seminar

22 The Next Generation CPLD
The Industry’s first 5V Flash CPLD Highest program/erase reliability of 10,000 cycles The best Pin-Locking CPLD architecture Most complete manufacturing and engineering JTAG support Support for the Total Product Life Cycle Technical seminar

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