1. EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design complex gates using nMOS/pMOS transistors

2. EE141 © Digital Integrated Circuits 2nd Devices 2 What is a Transistor? A Switch! |V GS | An MOS Transistor

3. EE141 © Digital Integrated Circuits 2nd Devices 3 The MOS Transistor Polysilicon Aluminum

4. EE141 © Digital Integrated Circuits 2nd Devices 4 CMOS devices

5. EE141 © Digital Integrated Circuits 2nd Devices 5 The NMOS  Substrate: lightly doped (p-)  Source and drain: heavily doped (n+)  Gate: polysilicon  Thin oxide separates the gate and the “channel”  Field oxide and field implant isolate the devices

6. EE141 © Digital Integrated Circuits 2nd Devices 6 MOS Transistors - Types and Symbols D S G D S G G S DD S G NMOS Enhancement NMOS PMOS Depletion Enhancement B NMOS with Bulk Contact

7. EE141 © Digital Integrated Circuits 2nd Devices 7 Threshold Voltage: Concept

8. EE141 © Digital Integrated Circuits 2nd Devices 8 Transistor in Linear

9. EE141 © Digital Integrated Circuits 2nd Devices 9 Transistor in Saturation Pinch-off

10. EE141 © Digital Integrated Circuits 2nd Devices 10 Summary of MOSFET Operating Regions  Strong Inversion V GS > V T  Linear (Resistive) V DS < V DSAT  Saturated (Constant Current) V DS  V DSAT  Weak Inversion (Sub-Threshold) V GS  V T  Exponential in V GS with linear V DS dependence

11. EE141 © Digital Integrated Circuits 2nd Devices 11 MOSFET equations  Cut-off region  Linear region  Saturation  Oxide capacitance/Gain Factor

12. EE141 © Digital Integrated Circuits 2nd Devices 12 Mobility

13. EE141 © Digital Integrated Circuits 2nd Devices 13 I D versus V GS 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V GS (V) I D (A) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) quadratic linear Long Channel Short Channel

14. EE141 © Digital Integrated Circuits 2nd Devices 14 MOS output characteristics  Linear region: V ds <V gs -V T  Voltage controlled resistor  Saturation region: V ds >V gs -V T  Voltage controlled current source  Curves deviate from the ideal current source behavior due to:  Channel modulation effects

15. EE141 © Digital Integrated Circuits 2nd Devices 15 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

16. EE141 © Digital Integrated Circuits 2nd Devices 16 Static Complementary CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … …

17. EE141 © Digital Integrated Circuits 2nd Devices 17 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

18. EE141 © Digital Integrated Circuits 2nd Devices 18 PMOS Transistors in Series/Parallel Connection

19. EE141 © Digital Integrated Circuits 2nd Devices 19 Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D

20. EE141 © Digital Integrated Circuits 2nd Devices 20 Complementary CMOS Logic Style

21. EE141 © Digital Integrated Circuits 2nd Devices 21 Example Gate: NAND

22. EE141 © Digital Integrated Circuits 2nd Devices 22 Example Gate: NOR

23. EE141 © Digital Integrated Circuits 2nd Devices 23 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

24. EE141 © Digital Integrated Circuits 2nd Devices 24 Constructing a Complex Gate

25. EE141 © Digital Integrated Circuits 2nd Devices 25 Cell Design  Standard Cells  General purpose logic  Can be synthesized  Same height, varying width  Datapath Cells  For regular, structured designs (arithmetic)  Includes some wiring in the cell  Fixed height and width

26. EE141 © Digital Integrated Circuits 2nd Devices 26 Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rails ~10 In Out V DD GND

27. EE141 © Digital Integrated Circuits 2nd Devices 27 Standard Cells In Out V DD GND InOut V DD GND With silicided diffusion With minimal diffusion routing

28. EE141 © Digital Integrated Circuits 2nd Devices 28 Standard Cells A Out V DD GND B 2-input NAND gate