1. CS-EE 481 Spring 2003 1Founder’s Day, 2003 University of Portland School of Engineering A CMOS Phase Locked Loop Authors: Dan Booth Jared Hay Pat Keller Advisor: Dr. Peter Osterberg Industry Representative: Mr. Steve Kassel (Ret.), Intel Corp.

2. CS-EE 481 Spring 2003 2Founder’s Day, 2003 University of Portland School of Engineering Agenda Introduction Dan Booth Background Dan Booth Methods Pat Keller Results Pat Keller Conclusions Jared Hay Demonstration Jared Hay

3. CS-EE 481 Spring 2003 3Founder’s Day, 2003 University of Portland School of Engineering Introduction Special Thanks –Dr. Peter Osterberg –Mr. Steve Kassel –Dr. Wayne Lu –Ms. Sandra Ressel –MOSIS Educational Program

4. CS-EE 481 Spring 2003 4Founder’s Day, 2003 University of Portland School of Engineering Introduction Project problem definition: –Synthesize 90-110kHz from a 1kHz reference Why frequency synthesis? –Frequency generator –Signal conditioning –Clock multiplication

5. CS-EE 481 Spring 2003 5Founder’s Day, 2003 University of Portland School of Engineering Introduction Goals –Understanding of our Phase Locked Loop: Architecture Operation Applications

6. CS-EE 481 Spring 2003 6Founder’s Day, 2003 University of Portland School of Engineering Background Phase Locked Loop Architecture Phase frequency detector Loop filter VCO Frequency Divider f in f out N Contro l CMOS Chip VCVC fdfd V error

7. CS-EE 481 Spring 2003 7Founder’s Day, 2003 University of Portland School of Engineering Background What our PLL frequency synthesizer does: –Produces an output of 90-110kHz in 1kHz increments f in = 1kHz N = integers from 90 to 110 f out = N*f in = 90 – 110kHz Key functional specifications: –f in and f out are 0 to 5 volt digital signals –Lock range of 90 – 110kHz

8. CS-EE 481 Spring 2003 8Founder’s Day, 2003 University of Portland School of Engineering Background Situation A: Frequencies are in phase - V C held constant Situation B: f in leads f d - V C increases Situation C: f d leads f in - V C decreases f in fdfd v error f in fdfd v error f in fdfd v error fdfd fdfd Phase Lock Feedback

9. CS-EE 481 Spring 2003 9Founder’s Day, 2003 University of Portland School of Engineering Methods Phase I: Research of PLLs

10. CS-EE 481 Spring 2003 10Founder’s Day, 2003 University of Portland School of Engineering Methods Phase II: Design of Chip B 2 Logic Simulations - Phase Frequency Detector - Frequency Divider Custom Design! TPR File - CMOS Chip Layout

11. CS-EE 481 Spring 2003 11Founder’s Day, 2003 University of Portland School of Engineering Methods Phase III: Building Macromodel of Chip VCO configuration - set control voltage range, V C - set output frequency range Loop Filter - 2 nd order low pass filter - set pole and zero for stability

12. CS-EE 481 Spring 2003 12Founder’s Day, 2003 University of Portland School of Engineering Methods Closing the feedback loop - Achieving lock User interface - N-Control switches - Seven-segment displays

13. CS-EE 481 Spring 2003 13Founder’s Day, 2003 University of Portland School of Engineering Results Digital CMOS Chip –Frequency Divider –Phase Frequency Detector =

14. CS-EE 481 Spring 2003 14Founder’s Day, 2003 University of Portland School of Engineering Results Off Chip Components –Loop Filter –Voltage Controlled Oscillator

15. CS-EE 481 Spring 2003 15Founder’s Day, 2003 University of Portland School of Engineering Conclusions CMOS Chip works! Operation is stable Increased Performance –Output range: 51 – 127kHz Limited by V C range of 0-5 V

16. CS-EE 481 Spring 2003 16Founder’s Day, 2003 University of Portland School of Engineering Conclusions Possible Improvements –Increase reference frequency accuracy Crystal oscillator Applications –Frequency generator –Signal conditioning –Clock multiplication

17. CS-EE 481 Spring 2003 17Founder’s Day, 2003 University of Portland School of Engineering Demonstration Power up f out displayed on scope - f out is N times f in - Lock is achieved quickly

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26. CS-EE 481 Spring 2003 26Founder’s Day, 2003 University of Portland School of Engineering Questions?