1. ISUAL Mass Memory Robert Abiad

2. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20012 Outline Description Requirements Interfaces Block Diagram Usage Scheme Parts Development Status

3. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20013 Description 2.6 GBit organized as 64 M x 40 bits 32 bit data word 7 bit Error Correction Code per word corrects all single bit errors and detects all double bit and some multiple bit errors. Samsung K4S560832A-TL1H 256 Mbit base device organized as 32M x 8bit.

4. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20014 Requirements Store data from Imager at 8M pixel/s data rate Store data from Array Photometer at 20k samples/s x 32 channels/sample = 640k channels/s Store data from Spectrophotometer at 10k samples/s x 6 channels/sample = 60k channels/s Read telemetry data at 1.6 Mb/s Allow read/write from DPU Allow read/write from DCM

5. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20015 Mass Memory Interfaces ImagerIDC/ Mass Memory DPU 12 DATA SP AP CLK ENA DATA-1 CLK ENA DATA-2 DATA ENA CLK DCM 32 2 DATA 26 ADDR BUSY 2 2 Telemetry CLK DATA

6. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20016 Priorities Imager Memory Refresh Telemetry Array Photometer Fast Spectrophotometer Slow Spectrophotometer DPU DCM

7. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20017 Mass Memory Block Diagram 32MB SDRAM Level Shift Level Shift Data Interface Address Interface Imager AP SP DPU DCM TLM

8. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20018 Usage Scheme Circular buffers Fill on trigger –N Pretrigger –M Posttrigger Buffer switch Buffer Allocation Trigger N M AA Buffer Allocation B

9. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 20019 SAMSUNG SDRAM Latch up immune up to 82 MeV/(mg/cm²) Radiation hardened to 17-40 kRad total dose SEU susceptibility mitigated by EDAC Parts received Parts will be lot tested to verify radiation tolerance

10. NCKU UCB Tohoku Mass Memory R. Abiad IFR 5-7 Mar 200110 Development Status Parts selection –All major parts ordered Usage schemes designed Address interfaces designed Memory controller designed Issues –FPGA speed limitations –FPGA device selection