1. BR 8/991 DFFs are most common Most programmable logic families only have DFFs DFF is fastest, simplest (fewest transistors) of FFs Other FF types (T, JK) can be built from DFFs We will use DFFs almost exclusively in this class –Will always used edge-triggered state elements (FFs), not level sensitive elements (latches).

2. BR 8/992 Synchronous vs Asynchronous Inputs Synchronous input: Output will change after active clock edge Asychronous input: Output changes independent of clock D Q C S R Flip-Flops often have async set, reset control. D input is synchronous with respect to Clk S, R are asynchronous. Q output affected by S, R independent of C. Async inputs are dominant over Clk. S,R inputs often called Pre (preset) and Clr (clear) inputs.

3. BR 8/993 DFF with async control C D input Q (FF) R S

4. BR 8/994 Flip-Flop, Latch Timing Propagation Delay –C2Q: Q will change some propagation delay after change in C. Value of Q is based on D input for DFF. –S2Q, R2Q: Q will change some propagation delay after change on S input, R input –Note that there is NO propagation delay D2Q for DFF! –D is a Synchronous INPUT, no prop delay value for synchronous inputs

5. BR 8/995 Clock to Q Propagation Delay C D input Q (FF) Tc2qlh Tc2qhl There is NO delay from D to Q!!! The clock input is what triggers the change, not the D input!!!

6. BR 8/996 S, R to Q Propagation Delay C D input Q (FF) S R Ts2qlh Tr2qhl

7. BR 8/997 Setup, Hold Times Synchronous inputs (e.g. D) have Setup, Hold time specification with respect to the CLOCK input Setup Time: the amount of time the synchronous input (D) must be stable before the active edge of clock Hold Time: the amount of time the synchronous input (D) must be stable after the active edge of clock.

8. BR 8/998 Setup, Hold Time (rising edge triggered) t su t hd C D changing Stable If changes on D input violate either setup or hold time, then correct FF operation is not guaranteed. Setup/Hold measured around active clock edge. D changing

9. BR 8/999 More on Setup, Hold Times C D changing Stable D changing The above setup/hold diagram are for a falling-edge triggered FF. Setup/Hold times are not equal to each other, a typical specification might be Tsu = 3 ns, Thd = 1ns.

10. BR 8/9910 Setup/Hold For JK FF t su t hd C J changing Stable J changing K changing Stable K changing Both J,K must satisfy setup/hold times

11. BR 8/9911 Only Synchronous Inputs have Tsu,Thd D Q C S R J Q C S R K S, R inputs are asynchronous inputs, no setup/hold times associated with them.

12. BR 8/9912 What do you have to know? Difference between Synchronous, Asynchronous inputs on FFs Propagation delays for FF, Latches Definition of Setup/Hold time