1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Nam Pham Van, Sebastian Kruse

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 2 Hex F900 0200 1E00 4200 5280 4200 … F900

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Hex F9 02 1E 42 528 42 … F9

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Hex F9 02 1E 42 528 Hex Binary F9 111110010 02 000000100 1E 000111100 42 010000100 528 010100101 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 111110010 02 000000100 1E 000111100 42 010000100 528 010100101

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 02 000000100 1E 000111100 42 010000100 528 010100101

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 02 000000100000000100 1E 000111100 42 010000100 528 010100101

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 02 000000100000000100 1E 00011110000100000 42 010000100 528 010100101

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 02 000000100000000100 1E 00011110000100000 42 010000100010000100 528 010100101

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Change of coefficients Slide 3 Reduce coefficients from 16 bits down to 9 bits  Less calculations by multiply operation Symmetric layout of coefficients  Only the first 5 coefficients have to compute Use of CSD-Recoding  Reducing of non-zero digits Hex Binary CSD (Canonical Sign Digit) F9 11111001000000010 02 000000100000000100 1E 00011110000100000 42 010000100010000100 528 010100101010100101

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Phase 2 – direct form II Slide 4 Direct form I Direct form II h(0) h(1) h(N-2) h(N-1) z -1 y(i) x(i) 0 h(0) h(1) h(N-2) h(N-1) z -1 0 x(i) y(i)

12. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Pipeline stages Slide 5 By using direct form II  8 pipeline stages are implemented Reducing of unnecessary bits 10 bit RCA for summation and multiplication 11 bit & 16 bit RCA for multiplication (5’th coefficient only) Separate the 5’th calculation into two pipeline stages

13. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Filter response Slide 6

14. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Slide 7 Mandatory values for FPGA Phase 1 (Synthese) Phase 2 (Place & Route) Frequency - f69,911 MHz 425,170 MHz Area - A (# of LUT-FF Pairs) 2215109 # Pipeline Stages18 Metric (MHz / LUT-FF Pairs) [0,032][3,900]

15. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Future improvements Change type of adder (phase 3)  Brent Kung adder  Han Carlson adder  Carry skip adder Only do an addition for important digits Summation compression (Wallace tree)  Carry save representation Slide 8

16. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 9