1. 1 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case Julian Lewis

2. 2 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case

3. 3 Master Slave configuration

4. GPS One pulse per Second GPS Symmetricom XLI PLL One pulse per Second Phase locked 10MHz Basic Period 1200/900/600 ms Advanced (100us)‏ One pulse per Second Synchronized 1KHz (slow timing clock)‏ Phase locked 10MHz Phase looked 40 MHz Event encoding clock 40MHz PLL Synchronization module in each timing generator crate RS485 Timing MTT Multitask Timing Generator MTT UTC time (NTP or GPS)‏ Event tables External events UTC Time and GPS CERN UTC Time Set once on startup & on Leap Seconds RS485 Timing CTR PPS 10 MHz 1 KHz 40MHz Delay Control System CERN UTC Time 25ns steps Timing receiver Symmetricom CS4000 portable Atomic Clock

5. 5 Multi-tasking module Two types of tasks System tasks for millisecond, external events, telegrams... Event table tasks Controlled across a FESA API FESA API allows... Load/Unload event table Run table N times Synchronize it with an event Run table for ever Stop table Abort table LHC GMT MT-CTG 16 16 Virtual CPUs produce the event output stream. The host front end system accesses MTT registers across VME bus (Beam Energy)‏ The VMEP2 permits hardware triggering tasks like PM event sending

6. Reads thresholds @1kHz-24Bit 10 8 Safe Machine Parameters Controller for LHC Energy A I_beam1 & 2 Reads status Energy B BEM BCT “A” BEM Management Critical Settings (CTRV) ‏ CTRV CTRx LSA BCT “B” EXP Line driver LHC Timing Generator SMP @ 10Hz 16Bit 10 10 (Flags, E & Int.)‏ BLM CTRV BLM CTRV BIS CTRV Kickers Timing Network Events, UTC, & Telegrams (including SMP)‏ Safe Machine Parameters Distribution BIS CTRx EXP Flags TTL Hw Output If length > 5m Beam Permit Flags BPF1/2

7. Current hardware status The SMP “mark-1” will be installed by week 15 (90% confidence)‏ There are as yet no Beam-Permit Flags wired to the timing, so we can't test PM/XPOC. Auto re-enable of Postmortem is waiting installation. Transmission delay calibration will start next week.

8. 8 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case

9. What is distributed on the LHC timing cable The LHC telegram Its main function is to continuously retransmit (shadow) information that has already been transmitted by events. Sent out each second, on the second. LHC machine events An event is sent punctually when something happens that affects the machine state. Some are asynchronous that come from external processes, e.g. post-mortems, energy, while others are produced from timing tables corresponding to running machine processes. Some are sent directly such as dump, commit transaction. The UTC time of day Resolution is 25ns, jitter is less than 1ns peak to peak, wonder is estimated to be around 10ns.

10. Some web addresses http://ab-dep-co-ht.web.cern.ch/ab-dep-co-ht/timing/Seq/tgm.htm This link shows the current telegram configuration. It also has information about the CTR hardware and other useful stuff. http://ab-dep-co-ht.web.cern.ch/ab-dep-co-ht/timing/Seq/mtgConfig.htm This link shows all defined timing events for the timing cables, and other useful stuff.

14. 14 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case

15. Postmortem Event generation Two Beam-Permit-Flags, one per LHC ring, arrive at the LHC central timing inputs from the Beam Interlock System. Beam-Dump events may be sent from the LHC central timing to the control system to dump the beam in one or other ring. The specification requires only one PM event for both rings. In some LHC machine modes such as “Inject & Dump”, sending the PM events will be inhibited. However the beam dumped events always go out. When both rings are dumped, the postmortem event is sent twice within 1ms.

16. Postmortem Event suppression Two counters are used in the CTR, one per Beam-Permit-Flag (BPF)‏ Each counter clock is connected to one of the BPF flags The "Disable Post-Mortem Ring 1" disables the counter connected to BPF-1 The "Enable Post-Mortem 1" enables the counter connected to BPF-1 When the counter is disabled and the BPF goes down nothing happens When its enabled the counter makes an output triggering the PM event It will be sent twice if both counters are enabled and both rings are dumped BPF1 BPF2 CTRCTG-MTT LHC GMT VME/P2 CLK Delay=1 Disabled CLK Delay=1 Enabled Disable-1, Enable-1 Dumped1/2 1 x (PM)‏ Disabled Enabled PM-1 Suppress Table Loads Warn-Inject LSEQ BPF1/2

17. Postmortem Event auto Re-Enable CTRCTG-MTT LHC GMT VME/P2 CLK Delay=2 Disabled CLK Delay=2 Enabled Disable1/2 Re-Enable PM-1 Suppress Table Warn-Inject BPF1/2 The Disable PM event also triggers a counter in a CTR In this case 2ms later an output pulse triggers the MTT to send PM enable event So the next BPF transition will trigger the PM event to be sent

18. 18 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case

19. 19 2.2 G-Bit / S optical link 64Mb Reflective memories CMW Server LHC MTG GMT LHC Clocks: 40.00 MHz GPS clock 1PPS (1Hz) clock Basic period clock Event Tables Safe Params Energy/Ring Intensity/Ring BIS Beam permit Flags External Events LSA High level Sequencer LSA Core FESA LHC API Slave/Master LHC Central Timing API

20. LSA and FESA The FESA API is implemented on the LHC timing gateway Accesses timing generators across reflective memory Implements Load or Unload event table Get running tables list Set event table run count and synchronization event Stop or Abort event table Set telegram parameters Send an event Read the status of tasks and MTT module

21. 21 LHC Beam Request BTNINext injection Beam Type Obviously the next injected beam type is determined by the settings in the injector chain and by nothing else. The LSEQ may request a certain type of beam to be injected, but if the requested value does not correspond to the actual beam type being provided by the injector chain, then the request can not be fulfilled and no injection can take place. This value is thus inherited from the injector chain BKNINext injection RF Bucket There are 35640 RF buckets around the LHC ring. It is essential that this parameter is established before RF re-synchronization starts between the CPS and the SPS RF systems, namely 450ms before CPS extraction towards the SPS RNGINext injection Ring This parameter determines the value of the SPS beam destination in the DEST group of the telegram. Various ways to do this are possible. Its an OP decision. BCNTNumber of CPS batches

22. 22 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case

23. 23

24. LHC Central Timing Generation CBCM Controlling Injector Chain Gateway FESA API LSA Timing Service SPS destination request R1,R2 CPS Batch Request 1,2,3,4 LIC Timing HIX.FW1K LHC Timing Inhibits Requests Interlocks SIS TI8/TI2 & SPS Dump Inhibits LHC Fill Requests: Bucket Ring Batches Master ON/OFF CTR LHC Fill Requests: Bucket Ring Batches Reflective Memory Link CBCM Sequence Manager LIC Sequence TI8/TI2 Dump Request TI8/TI2 Dump LHC User Request LHC User Normal Spare LSA changes Allowed LSA Master SEX.FW1K SPS.COMLN.LSA_ALW LHC – LIC Signal Exchange

25. 25 Linac PSB CPS SPS D3 Dump TI8 Dump TI2 Dump SPS Dump TI8 TI2 CNGS TCLP Default when no LSEQ request and LSEQ is master Default when no TI8/2 dump and LSEQ is not master Only possible when SIS dump status is “IN” and requested Only possible when LSEQ is master and no TI8/2 SIS inhibits Default when no batches were requested and LSEQ is master LEIR

26. CBCM Sequence Manager

27. PSB1 PSB2 PSB3 PSB4 CPS Batch 1CPS Batch 2CPS Batch 3CPS Batch 4 SPS Cycle for the LHC SPS injection plateaux The LHC Beam LSA Beam request: RF bucket Ring CPS batches Extraction Forewarning LHC Injection plateaux Injection Extraction The LHC timing is only coupled by extraction start-ramp event Extraction Forewarning

28. 28 PSB1 PSB2 PSB3 PSB4 CPS Batch 1CPS Batch 2CPS Batch 3CPS Batch 4 SPS Cycle for the LHC SPS injection plateaux The LHC beam Operators mark the SPS cycle as “TOLHC” Inheritance mechanism propagates “TOLHC” to all cycles in the beam LSEQ Control affects the way “TOLHC” beams are played The SPS telegram contains a new “DYNAMIC” destination calculated on the fly TI8/TI2/TI8_DMP/TI2_DMP/SPS_DMP/CNGS/FT The CBCM evaluates LHC beam requests 1.2 seconds before the first PSB cycle in the CBCM time domain. The CBCM time domain is 2.4 seconds ahead of the accelerator complex time domain. So the request must be 3.6 seconds ahead. Any bad condition will provoke the spare response as usual. “TOLHC”

29. 29 Killing a “TOLHC” batch The Linac Tail-Clipper timing cuts 99% of the beam at the Linac. The PSB plays the cycle with no or very little beam. The CPS destination is forced from the SPS to D3 The SPS cycle continues as usual, but no CPS beam is injected, destination is the internal dump. The SPS injection timing for the suppressed batch fires anyway. TCLP D3 Dump

30. 30 Basic behavior TOLHC 1.Any abnormal interlock drives the beam into spare. This may result in SPS going in to economy mode. N.B. TI8 dump or TI2 dump are only possible when the dump status (From SIS) indicates that the dumps are in place. TI8TI2 TI8/2 TI8 or TI2 destinations are only possible when LSEQ is master, and when there is a valid LSEQ beam request, and there are no TI8/2 SIS inhibits. SPS dumpTI8TI2 When LSEQ is not the master the default destination is the SPS dump. A TI8 or TI2 dump can be requested. The number of CPS batches delivered is controlable. When LSEQ is master and there is no request, the beam is killed, but the magnetic cycle takes place. Mastership can only be changed in the absence of the LHC User request

31. 31 Nominal fill Use case 1 Prepare injector chain LHC operator asks SPS operator to prepare to fill the LHC. SPS LHC cycle request. SPS operator removes the SPS LHC cycle request. SPS dump If we don’t want to deliver the beam to the SPS dump straight away. – LSEQ mastership can not be changed while the LHC beam is playing !!! SPS operator loads/runs the LHC fill sequence. The BCD starts up with LHC beams in spare, and the SPS may be in economy mode.

32. 32 Nominal fill Use case 2 Beam to TI8/TI2 Dumps TI8/TI2 dump SPS operator want to send the beam to a TI8/TI2 dump LSEQ is not the master OP sets the dump targets to move into place and waits (Minutes) TI8/TI2 dump request OP selects TI8/TI2 dump request external conditions on central timing. LHC user request OP sets LHC user request on. OP sets the CPS batch count to N TI8/TI2 N x CPS batches are now sent to a TI8/TI2 dump

33. 33 Nominal fill Use case 3 Beam to SPS dump OP want to send the beam to SPS dump. LSEQ is not the master TI8/TI2 Dump requests The TI8/TI2 Dump requests must be removed. LHC User request The LHC User request must be present SPS dump N CPS batches are now delivered to the SPS dump

34. 34 Nominal fill Use case 4 LSEQ takes mastership LSEQ now wants to become master. LHC user request – The LHC user request must be removed. – The current SPS super-cycle will finish and then the LHC beam is spared (Economy Mode)‏ The SPS telegram bit SPS.COMLN.LSEQ_ALW gets set by the CBCM. LSEQ calls the API to request mastership. If SPS.COMLN.LSEQ_ALW isn’t ready, an error is returned. LSEQ becomes master, and the LHC user request is turned back on by SPS operations. All beams are played in normal but TCLP, D3 insure there is no beam injected into the SPS. The SPS destination is SPS dump, and there is no extraction timing.

35. 35 Nominal fill Use case 5 LSEQ Sends beam to LHC LSEQ wants to send beam to the LHC LSEQ must be the master TI8/2 There must be no TI8/2 SIS inhibits. LHC user request LHC user request must be asserted LSEQ makes a request for 1/2/3/4 batches to ring 1/2 bucket N On the next SPS super cycle the request is executed, then cleared.

36. 36 LIC – LHC filling It would be a good idea to test the fill use case out in a dry-run once all cabling and hardware installation has been completed. LSEQ Takes mastership Makes a beam request PM Enable/Disable with BPF transitions