1. 55:035 Computer Architecture and Organization Lecture 2

2. Outline  Information representation  Arithmetic operations (addition and subtraction)  Instruction Formats  Addressing Modes  Assembly Language Programming  Basic input/output operations  Subroutine linkage 255:035 Computer Architecture and Organization

3. Integer non-Negative Number Representation The most significant bitThe least significant bit 355:035 Computer Architecture and Organization

4. Decimal-to-Binary Conversion V is divided by 2  the reminder is the least significant bit of B b n b n-1 …b 1 b 0 The quotient is again divided by 2  the reminder is the next bit of B b n b n-1 … b 1 b 0 … The process is repeated up to and including the step in which the quotient becomes 0: b n b n-1 …b 1 b 0 455:035 Computer Architecture and Organization

5. Real non-Negative Number Representation 555:035 Computer Architecture and Organization

6. Decimal-to-Binary Conversion To convert a fixed-point decimal number into binary, the integer and fraction parts are handled separately. The integer part is converted as the integer number The fractional part is converted by multiplying it and then fractional parts of its products by 2: The part of the product to the left of the decimal point, which is either 0 or 1, is a bit in the binary representation. The first bit generated is the bit immediately to the right of the binary point. The next bit generated is the second bit to the right, and so on The process is repeated until the required accuracy is attained 655:035 Computer Architecture and Organization

7. 927 2 ---------463 1 2 ---+= 2 ---------231 1 2 ---+= 2 ---------115 1 2 ---+= 2 ---------57 1 2 ---+= 2 ------28 1 2 ---+ = 2 ------14 0 2 ---+= 2 ------7 0 2 ---+= 7 2 ---3 1 2 ---+= 3 2 ---1 1 2 ---+ = 1 2 ---0 1 2 ---+ = 1 LSB 1 MSB 1 1 1 1 0 0 1 1 0.452  0.90= 2  1.80= 0.802  1.60= 0.602  1.20= 0.202  0.40= 2  0.80= 2  1.60= 0 MSB 1 LSB 1 1 1 0 0 Convert 927.45  10 1110011111.0111001  2 = 927.45  10 755:035 Computer Architecture and Organization

8. Signed Numbers Representation  The leftmost bit b n-1 is the sign bit:  0 for positive numbers and 1 for negative numbers Positive values have identical representation Negative values have different representation 855:035 Computer Architecture and Organization

9. Signed Numbers Representation Sign-and-magnitude representation (negative values are represented by changing the most significant bit): +5 = 0101-5 = 1101 1’s-complement representation (negative values are obtained by complementing each bit of the corresponding positive number): +5 = 0101-5 = 1010 2’s-complement representation (negative values are obtained by subtracting the corresponding positive number from 2 n ): 955:035 Computer Architecture and Organization

10. Signed Numbers Representation 1055:035 Computer Architecture and Organization

11. Figure 2.2. Addition of 1-bit numbers. Carry-out 1 1 + 011 0 1+ 0 0 0 + 1 0 1 + Addition of Positive Numbers 1155:035 Computer Architecture and Organization

12. S/M and 1’s-Complement Representation  Since we can’t perform addition and subtraction in the same manner, development of special circuitry for subtraction is needed  1’s-Complement Representation does not allow a universal representation of 0: there are +0 and -0 that become formally different values 1255:035 Computer Architecture and Organization

13. 2’s Complement Conversion to Decimal Positive Numbers: Just ignore the 0, repeat the process studied earlier. For negative numbers: Example 1101 Discard the 1 which represents the sign: 101 Subtract 1 101 100 Complement 100=>011 Obtain decimal value (011) B =3 D Remember is a negative value 1101 = -3 1355:035 Computer Architecture and Organization

14. Decimal Conversion to 2’s Complement Positive Numbers Find signed representation Negative numbers Subtract number from 2 n Find signed representation 1455:035 Computer Architecture and Organization

15. Addition of 2’s-Complement Numbers To add two numbers, add their n-bit representations, ignoring the carry-out signal from the most significant bit (MSB) position. Note: The sum will be correct in the 2’s complement representation as long as the answer is in the range -2 n-1 through 2 n-1 -1 1555:035 Computer Architecture and Organization

16. Subtraction of 2’s-Complement Numbers To subtract two numbers X and Y, that is, to perform X-Y, form the 2’s-complement of Y and then add it to X according to the addition rule. Note: The result will be correct in the 2’s complement representation as long as the answer is in the range -2 n-1 through 2 n-1 -1 1655:035 Computer Architecture and Organization

17. Figure 2.3. Modular number systems and the 2's-complement system. N2- N1- 0 1 2 (a) Circle representation of integers mod N 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1+1- 2+ 3+ 4+ 5+ 6+ 7+ 2- 3- 4- 5- 6- 7- 8- 0 (b) Mod 16 system for 2 ' s-complement numbers 2’s Complement System 1755:035 Computer Architecture and Organization

18. Addition of 2’s-Complement Numbers 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 +1 +2 +3 +4 +5 +6 +7 -2 -4 -5 -6 -7 -8 0 -3 3+2=5; 3 ’2 =0011; 2 ’2 =0010 3| 0011 + 2| +0010 5| 0 0101 Carry-out bit is ignored to obtain the correct result Good method as long as the results is less than 2 (N-1) -1 1855:035 Computer Architecture and Organization

19. Addition of 2’s-Complement Numbers 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 +1 +2 +3 +4 +5 +6 +7 -2 -4 -5 -6 -7 -8 0 -3 7-3=4; 7 ’2 =0111; -3 ’2 =1101 (if this were an unsigned number 1101=13) 7 | 0111 +(-3)| +1101 (8 -3= 5=> 1 101) 4| 10100 Carry-out bit is ignored to obtain the correct result 1955:035 Computer Architecture and Organization

20. 2’s-Complement Addition  The 2’s-Complement System is the most efficient for addition and subtraction of signed numbers because both can be performed in the same manner for both positive and negative numbers  Same manner=Same circuitry=Less $$$$ 2055:035 Computer Architecture and Organization

21. Overflow in Integer Arithmetic  In the 2’s-complement system n bits can represent the values in the range  For example:  When the result of an arithmetic operation is outside this range, an arithmetic overflow has occurred 6| 0110 5| +0101 11|= 1011 overflow -7| 1001 1001 +( -1)| -0001  1111 -8|=11000 no overflow 2155:035 Computer Architecture and Organization

22. Overflow in Integer Arithmetic  A simple way to detect overflow is to examine the signs of the two summands (X and Y ) and the sign of the result S (S=X+Y).  When both operands X and Y have the same sign, an overflow occurs if the sign of sum S is not the same as the signs of X and Y.  Overflow can occur only when adding two numbers that have the same sign  The carry-out signal from the sign-bit position is not a sufficient indicator of overflow when adding signed numbers 2255:035 Computer Architecture and Organization

23. 1 0 1 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 1 1 5-  2+() 3+ () 5+() 2+() 4+ () 2-  7-  3-  7-  6+() 3+() 1+() 7-  5-  7-  2+() 3-  6-  2-  4+() 3-  4+() 7+ () 4+() 2-  3+() 2-  8-  5+ () + + + + + + + + + + - - - - - - (a) (c) (b) (d) (e) (f) (g) (h) (i) (j) 2’s-Complement Addition and Subtraction 2355:035 Computer Architecture and Organization

24. Comparison of Signed Representations 2455:035 Computer Architecture and Organization

25. Character Representation  Each character is encoded by 8 bits  American Standards Committee on Information Interchange (ASCII) encoding system – 7 bits encoding  The 8 th (most significant) bit is used to encode characters from different alphabets and some extra special symbols 2555:035 Computer Architecture and Organization

26. Encoding of decimal digits Decimal digit BCDcode 00000 10001 20010 30011 40100 50101 60110 70111 81000 91001 Binary Coded Decimal (BCD) 2655:035 Computer Architecture and Organization

27. Hexadecimal Numbers  Base 16 ={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}  (Z 3 Z 2 Z 1 Z 0 ) H = (Z 3 x 16 3 )+(Z 3 x 16 2 )+(Z 3 x 16 1 )+(Z 3 x 16 0 )= (Z 3 x4096)+(Z 3 x 256)+(Z 3 x 16)+(Z 3 x 1)  Example: (A34E) H = (A x 16 3 )+(3 x 16 2 )+(4 x 16 1 )+(E x 16 0 )= (Ax4096)+(3x 256)+(4x 16)+(E x 1)= (10x4096)+(3x 256)+(4x 16)+(14 x 1)= 40960+768+64+14=41806. 2755:035 Computer Architecture and Organization

28. Hexadecimal Numbers Advantages  Easier to represent large numbers in compact manner  Close relationship to binary numbers Ex.: Find the binary representation of 110101101011101 110 1011 0101 1101 6 D =6 H 11 D =B H 5 D =5 H 13 D =C H (110101101011101) B =(6B5C) H 2855:035 Computer Architecture and Organization

29. Conversion Hexadecimal-Decimal  Hexadecimal to Decimal: As shown on previous slide  Decimal to HEX: Same process as with binary. Example: (1574) D =(?) H 1974 / 16 = 123 rem 6 123 / 16 = 7 rem 11 Hence (1574) D =(7B6) H 2955:035 Computer Architecture and Organization

30. Table of ASCII Characters CharHexCharHexCharHexCharHex (nul)0x00(sp)0x20@0x40`0x60 (soh)0x01!0x21A0x41a0x61 (eot)0x04$0x24D0x44d0x64 (enq)0x05%0x25E0x45e0x65 (ack)0x06&0x26F0x46f0x66 (bel)0x07'0x27G0x47g0x67 (bs)0x08(0x28H0x48h0x68 (ht)0x09)0x29I0x49i0x69 (nl)0x0a*0x2aJ0x4aj0x6a (vt)0x0b+0x2bK0x4bk0x6b (cr)0x0d-0x2dM0x4dm0x6d (so)0x0e.0x2eN0x4en0x6e (si)0x0f/0x2fO0x4fo0x6f (dle)0x1000x30P0x50p0x70 (dc1)0x1110x31Q0x51q0x71 (dc2)0x1220x32R0x52r0x72 (dc3)0x1330x33S0x53s0x73 (dc4)0x1440x34T0x54t0x74 (nak)0x1550x35U0x55u0x75 (syn)0x1660x36V0x56v0x76 (etb)0x1770x37W0x57w0x77 (can)0x1880x38X0x58x0x78 (em)0x1990x39Y0x59y0x79 (sub)0x1a:0x3aZ0x5az0x7a (fs)0x1c<0x3c\0x5c|0x7c (gs)0x1d=0x3d]0x5d}0x7d (rs)0x1e>0x3e^0x5e~0x7e (us)0x1f?0x3f_0x5f(del)0x7f 3055:035 Computer Architecture and Organization

31. Minimum Number of Bits  55:035 Computer Architecture and Organization31

32. Memory Cells ………………. Each cell can store 1 bit of information having the value 0 or 1 3255:035 Computer Architecture and Organization

33. Memory Word is a group of n bits … n is called the word length … 0n-1 Modern computers have word length that typically range from 16 to 64 bits As a rule, the word length is a power of 2: 16, 32 or 64 bits 3355:035 Computer Architecture and Organization

34. Memory Byte is a unit of 8 bits … Word typically consists of 2 or 4 bytes (2 bytes for the IBM PC) … 07 Bits are seldom addressable individually Bytes have addresses that are used for accessing the memory to store or retrieve a single item of information 3455:035 Computer Architecture and Organization

35. Byte Addressability Successive byte locations in the memory have successive addresses Memory is byte-addressable Thus, successive byte locations have addresses 0, 1, 2, 3, 4,… If the word length of the machine is 32 bits, successive words are located at the aligned addresses 0, 4, 8, 12, … 3555:035 Computer Architecture and Organization

36. second word (4) first word (0) n bits last word i th word Memory 3655:035 Computer Architecture and Organization

37. (b) Four characters character (a) A signed integer Sign bit: for positive numbers for negative numbers ASCII 32 bits 8 bits b 31 b 30 b 1 b 0 b 31 0= b 1= Encoded Information 3755:035 Computer Architecture and Organization

38. Memory Usually numbers from 0 through 2 k -1 for some suitable value of k are used as the addresses of successive locations (bytes) in the memory The 2 k addresses constitutes the address space of the computer, and the memory has up to 2 k addressable locations 3855:035 Computer Architecture and Organization

39. Example  k=3 then we can access 2 3 =8 different addresses: BinaryDecimal 0000 0011 0102 0113 1004 1015 1106 1117 3955:035 Computer Architecture and Organization

40. Memory Units Example: 24-bit address generates an address space of 2 24 =2 4 x 2 20 bytes = 16 x 1M= 16 M (Megabytes) Example: 32-bit address generates an address space of 2 32 bytes =2 2 x 2 30 = 4 x 1 G = 4 (Gigabytes) 1M (Mbyte) = 2 20 (1,048,576) bytes = 1,024 K 1G (Gbyte) = 2 30 bytes = 1,024 M 1K (Kbyte) = 2 10 (1,024) bytes 1T (Tera) = 2 40 bytes = 1,024 G 4055:035 Computer Architecture and Organization

41. Memory Units What if we want to address 3,000,000 bytes? 2 22 bytes =2 2 x 2 20 = 4 x 1 M = 4 M > 3,000,000 bytes 2 21 bytes =2 1 x 2 20 = 2 x 1 M = 2 M < 3,000,000 bytes Not enough addresses! 4155:035 Computer Architecture and Organization

42. Addresses Assignment  Big-endian assignment: lower byte addresses are used for the more significant (the leftmost) bytes of the words  Little-endian assignment: lower byte addresses are used for the less significant (the rightmost) bytes of the words 4255:035 Computer Architecture and Organization

43. 2 k 4-2 k 3-2 k 2-2 k 1-2 k 4-2 k 4- 0123 4567 0 0 4 2 k 1-2 k 2-2 k 3-2 k 4- 3210 7654 Byte address (a) Big-endian assignment(b) Little-endian assignment 4 Word address Addresses Assignment 4355:035 Computer Architecture and Organization

44. Debug Characteristics: Is program provided by DOS Used for testing and debug executable programs Displays all program code and data in hexadecimal Allows to execute programs step by step Does not distinguish between lowercase and upper case Commands: D Display the contents of an area in memory E Enter data into memory Q Quit session R Display the contents of one or more registers T Trace the execution of one instruction W Write program onto disk 4455:035 Computer Architecture and Organization

45. Debug Display Hex Address Hex Representation ASCII Representation 4555:035 Computer Architecture and Organization

46. Debug Display System Equipment (54) 16 =“T” same 4655:035 Computer Architecture and Organization

47. Debug Display Memory Size Little- Endian Byte Swap Decimal 80 02 02 80640 k 4755:035 Computer Architecture and Organization

48. Debug Display Model ID FC = PC-AT 4855:035 Computer Architecture and Organization

49. Machine Instructions  A computer must have instructions capable of performing four types of operations: Data transfers between the memory and the processor registers Arithmetic and logic operations on data Program sequencing and control Input/Output (I/O) transfers 4955:035 Computer Architecture and Organization

50. Data Transfers: Possible Locations  Memory locations  Processor registers  Registers in the I/O subsystem  In the instruction itself (immediate data) Most of the time we identify a location by a symbolic name standing for its hardware binary address: Memory Locations: LOCA, LOC, PLACE, A, VAR2, JOHN_SMITH Processor register names: R0, R5, R10, … I/O register names: DATAIN, OUTSTATUS 5055:035 Computer Architecture and Organization

51. Data Transfers: Register Transfer Notation The contents of a location are denoted by placing square brackets around the name of the location: [LOC] means the contents of the location LOC R1  [LOC] means that the contents of memory location LOC are transferred into processor register R1 R3  [R1]+[R2] means that the sum of the contents of registers R1 and R2 is transferred into processor register R3 5155:035 Computer Architecture and Organization

52. Data Transfers: Assembly Language Notation Move LOC, R1 means that the contents of memory location LOC are transferred into processor register R1 This is equivalent to R1<- [LOC] in Register Transfer Notation In the IBM PC the instruction MOV is equivalent to Move (more about this later)! 5255:035 Computer Architecture and Organization

53. Data Transfers: Assembly Language Notation Move Source, Destination means that the contents of memory location Source are transferred into memory location Destination. As a result, the previous contents of memory location Destination will be replaced, but the contents of memory location Source will not be changed The instruction Move copies the contents of one memory location to another one 5355:035 Computer Architecture and Organization

54. What is “Standard” Assembly? Book: ”Standard” Assembly Language Format OPcode src, dst IBM PC Assembly Real-life Assembly Language Format OPcode dst, src 5455:035 Computer Architecture and Organization

55. MOV Instruction Remember that the IBM PC assumes that you are talking about the contents of a variable (Move), not its memory address (  ), hence, if: X is a variable with memory address 10H and its contents are 24H 1)The instruction: MOV AX,X moves 24H into AX 2) The instruction MOV AX,[X] moves 87H into AX 24 87 Address: 10H Address: 24H 5555:035 Computer Architecture and Organization

56. Basic Instruction Types C=A+B How is this high-level language command implemented in the computer? To carry out the action C  [A]+[B] the contents of memory locations A and B are fetched from memory and transferred into the processor, where their sum is computed and then transferred to memory location C 5655:035 Computer Architecture and Organization

57. Three-Address Instruction General form: Operation Source1, Source2, Destination Add A, B, C Disadvantage: This form has 3 operands. If memory addresses were to be used to specify operands, the memory space would be very limited. Example: if k=10 bits (enough for a memory of 1 KB), then 30 bits will be needed for the 3 operands. 5755:035 Computer Architecture and Organization

58. Two-Address Instruction General form: Operation Source, Destination An Add instruction: Add A, B performs the operation B  [A]+[B]. When the sum is calculated, the result is sent to memory and stored in location B, replacing the original contents of this location. C  [A]+[B] can be implemented as Move B, C Add A, C Even a 2-address instruction is too large for a processor with a 32-bit address space ! 5855:035 Computer Architecture and Organization

59. One-Address Instruction Examples: Add A means: Add the contents of memory location A to the contents of the accumulator register and place the sum back into the accumulator Move A means: Copy the contents of memory location A to the accumulator register Store A means: Copy the contents of the accumulator register to memory location A General form: Operation Source 5955:035 Computer Architecture and Organization

60. One-Address Instruction Thus, C  [A]+[B] can be implemented as (Assembly Language) Move A Add B Store C which means (Register Notation): Accumulator  [A] Accumulator  [Accumulator] + [B] C  [Accumulator] Notice that now the 32-bits will be use only to access 1 memory location and to denote the operation A two-operand instruction, how is it possible? One Register, One memory location 6055:035 Computer Architecture and Organization

61. One-Address Instruction In the IBM PC, C  [A]+[B] can be implemented as ;Assembly Language Register Notation MOVAX,A ; [AX]  [A] ADDAX,B; [AX]  [AX] + [B] MOVC,AX ; [C]  [ AX] Notice that in the IBM PC Assembly Language the operation “addition” is represented by the instruction “ADD”. The symbol “;” is used to indicate the start of comments. Comments are useful to remind us what the program is doing, but they do NOT effect the behavior of it 6155:035 Computer Architecture and Organization

62. Processor Registers Because the number of registers is relatively small, only a few bits are needed to specify, which register takes part in an operation For example, for 32 registers only 5 bits are needed to address them (while 8 bits are needed to address a single byte in the memory) This makes it possible to use “two”- and “three”- address instructions 6255:035 Computer Architecture and Organization

63. Using Processor Registers for Arithmetic Operations C=A+B that is, C  [A]+[B] can be implemented as Move A, R i MoveB, R j Add R i, R j MoveR j, C 4 instructions If we wanted to do it in this manner, for the IBM PC we would have: MOVDX,A MOVAX,B ADDAX,DX MOVC,AX 6355:035 Computer Architecture and Organization

64. If One of the Arithmetic Operands is in Memory C=A+B that is, C  [A]+[B] can be implemented as Move A, R i Add B, R i Move R i, C 3 instructions For the IBM PC we would have: MOVAX,A ADDAX,B MOV C,AX 6455:035 Computer Architecture and Organization

65. Addressing Modes 6555:035 Computer Architecture and Organization

66. Program Sequencing and Control Programs aren’t all “in-line”, they also need to:  jump to and from subroutines  loop  branch to exception vectors  etc Use call and branch instructions Can be conditional  Branch > 0 LOOP Control instruction examples  cache control, pipeline control, RFI, WFI 6655:035 Computer Architecture and Organization

67. Specific Machine Levels 6755:035 Computer Architecture and Organization

68. Translating Languages English: Display the sum of A times B plus C. C++: cout << (A * B + C); Assembly Language: mov eax,A mul B add eax,C call WriteInt Intel Machine Language: A1 00000000 F7 25 00000004 03 05 00000008 E8 00500000 6855:035 Computer Architecture and Organization

69. Assembly Language  Mnemonics, symbolic names, and rules for their use for a specific computer type  For example: Operation: MOV, ADD, INC, BR Register or Memory: R2 or LOC Syntax: ADDI 5,R3  Viable programming language(s) Very good control of the machine Albeit cumbersome! 6955:035 Computer Architecture and Organization

70. Assembly Language  No standard format  Assembly language is converted into machine instructions (1’s and 0’s) by a program called an Assembler  Assembler Directives provide other information to the assembler where to place instructions where to put data constant values 7055:035 Computer Architecture and Organization

71. Assembly Language Example MemoryAddressing addressordata labelOperationinformation Assembler directivesSUMEQU200 ORIGIN204 NDATAWORD100 NUM1RESERVE400 ORIGIN100 Statements thatSTARTMOVEN,R1 generateMOVE#NUM1,R2 machineCLRR0 instructionsLOOPADD(R2),R0 ADD#4,R2 DECR1 BGTZLOOP MOVER0,SUM RETURN ENDSTART Assembler directives 7155:035 Computer Architecture and Organization NUM2 NUMn NUM1 R0Clear R0,SUM R1 #4,R2 (R2),R0 100 132 604 212 208 204 200 128 124 120 116 112 108 104 100 SUM N LOOP Decrement Add Move #NUM1,R2 N,R1Move Branch>0

72. Basic I/O READWAITTestbit#3,INSTATUS Branch=0READWAIT MoveByteDATAIN,R1 WRITEWAITTestbit#3,OUTSTATUS Branch=0WRITEWAIT MoveByteR1,DATAOUT DATAINDATAOUT SINSOUT KeyboardDisplay Bus Processor 7255:035 Computer Architecture and Organization

73. Queues / FIFOs  First In — First Out Buffer data between two entities:  Keyboard => Processor  Processor => Printer  Processor1 => Processor2 Scheduling as well:  Printer queue  Queue of processes for multi-tasking  Event queue in VerilogHDL Queues may use priority ranking 55:035 Computer Architecture and Organization73

74. Queues / FIFOs  First In — First Out The two basic functions are:  APPEND an element on one end  REMOVE an element from the other Frequently, one entity appends items to the queue and another removes it Two moving pointers are needed:  IN: location for next APPEND  OUT: location for next REMOVE Wrap-around is needed 55:035 Computer Architecture and Organization74

75. Queues / FIFOs  Pointers usually managed by hardware  Overflow occurs when an element is appended to a full queue  Underflow occurs when an element is removed from an empty queue  May have Empty, Almost Full, Full flags 55:035 Computer Architecture and Organization75

76. Stacks/LIFOs  Last In — First Out Stacks are used to temporarily store items The two basic functions are:  PUSH an element on the top  POP the top element from the stack Frequently, the same entity that pushed the item on stack also pops it In contrast to the queue  Only one pointer needed – it points to the top element  PUSH and POP in different directions  Wrap-around is not needed 55:035 Computer Architecture and Organization76

77. Stacks/LIFOs  Processor Stack Dedicated Stack Pointer (SP) SP may be a general-purpose register SP “grows” towards smaller addresses Implementation of stack operations: PUSH: Move NewItem, -(SP) SP <- [SP] - 1, [SP] <- NewItem POP: Move (SP)+,TopItem TopItem <- [[SP]]; SP <- [SP] + 1 55:035 Computer Architecture and Organization77

78. Subroutines  Program segments may occur repeatedly: 55:035 Computer Architecture and Organization78

79. Subroutines  Solution: Call a subroutine multiple times  Problems: Return address needs to be known! How to pass parameters? Where to keep local variables? 55:035 Computer Architecture and Organization79

80. Subroutine Calling  Link register: Call SUB LR <- [PC] PC <- SUB Return PC <- [LR]  Address on stack: Call SUB SP <- [SP] – 1 [SP] <- [PC] PC <- SUB Return PC <- [[SP]] SP <- [SP] + 1 55:035 Computer Architecture and Organization80

81. Parameter Passing Stored in a designated memory area: MAINMoveparX, AAddSubMoveA, R0 MoveparY, BAddB, R0 CallAddSubMoveR0, C MoveC, ResultReturn Stored in designated registers: MAINMoveparX, R0AddSubMoveR0, R2 MoveparY, R1AddR1, R2 CallAddSubReturn MoveR2, Result Using the stack: MAINMoveparX, -(SP)AddSub? MoveparY, -(SP)… CallAddSubReturn Move?, Result 55:035 Computer Architecture and Organization81

82. Parameter Passing through Stack Simple Example Re-Using Parameter Space: MAINMovePARAM1, -(SP); push Param1 MovePARAM2, -(SP); push Param2 CallSUBR; call subroutine Move(SP), RESULT; get return value Add#8, SP; clean up stack SUBRMove8(SP), R0; load Param 1 Add4(SP), R0; add Param 2 MoveR0, 4(SP); store result Return; Result = P1 + P2 55:035 Computer Architecture and Organization82

83. Parameter Addressing  Remember that Return Address in on the Stack Too: Assumptions:  two 32-bit parameters, no temporary items on stack, result size is 32-bit, result replaces parameter 55:035 Computer Architecture and Organization83

84. Subroutine Linkage  Call instruction is used to call a subroutine  Subroutine returns control to the calling program when it is done  Stack is used to pass information ReturnCall 1000 204 Link PC Return 1000 location Memory Calling program Memory location 200 204 Call SUB next instruction Subroutine SUB first instruction 8455:035 Computer Architecture and Organization

85. Subroutine Linkage Call pushes information onto stack Return pops information off of stack Stack pointer (SP) and Frame pointer (FP) used to access parameters and variables SP (stack pointer) FP (frame pointer) saved [R1] saved [R0] Stack frame for called subroutine Return address localvar3 localvar2 localvar1 saved [FP] Old TOS param2 param1 param3 param4 (top-of-stack) 8555:035 Computer Architecture and Organization