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Design & Co-design of Embedded Systems Data Types in SystemC Maziar Goudarzi
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2005 Design & Co-design of Embedded Systems2 Today Program zBit-accurate data types provided by SystemC zUser-defined data types
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Data Types in SystemC Data Types
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2005 Design & Co-design of Embedded Systems4 Data Types zSystemC data types ySingle-bit Types xsc_bit, sc_logic yInteger Types xsc_int, sc_uint, sc_bigint, sc_biguint yBit-Vector Types xsc_bv, sc_lv yFixed-Point Types xsc_fixed, sc_ufixed, sc_fix, sc_ufix
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2005 Design & Co-design of Embedded Systems5 Data Types (cont’d) zDefined for all types yStreaming operator defined for all types xostream& operator << ( ostream&, T ); xExample sc_bit b; cout<<b; yTrace function xsc_trace(,, ) xExample sc_bit b; sc_trace( tf, b, “message”);
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2005 Design & Co-design of Embedded Systems6 Single-bit Types zsc_bit yTwo-valued logic: ‘0’, ‘1’ (character literal) yExample: sc_bit b; b=‘1’; // the same as b=1 or b=true b=‘0’; // the same as b=0 or b=false yDefined operators xBitwise:&(and)|(or)^(xor)~(not) xAssignment:=&=|=^= xEquality:==!=
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2005 Design & Co-design of Embedded Systems7 Single-bit Types (cont’d) zsc_logic yFour-valued logic: ‘0’, ‘1’,‘X’,‘x’,‘Z’,‘z’ (char. literal) x‘x’ means unknown or indeterminate value x‘z’ means high impedance or floating value yExample: sc_logic l; l=‘0’; // the same as l=0, false, sc_logic_0 l=‘1’; // the same as l=1, true, sc_logic_1 l=‘z’; // the same as l=2, sc_logic_Z l=‘x; // the same as l=3, sc_logic_X
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2005 Design & Co-design of Embedded Systems8 Single-bit Types (cont’d) zsc_logic (cont’d) yDefined operators xBitwise:&(and)|(or)^(xor)~(not) xAssignment:=&=|=^= xEquality:==!=
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2005 Design & Co-design of Embedded Systems9 Single-bit Types (cont’d) zAny mixture of sc_bit, sc_logic, and bool types in comparison and assignments is possible, except: sc_logic k; sc_bit b; // or bool b k = ‘z’; // or k = ‘x’ b = k; // Result is undefined. // Run-time warning is issued
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2005 Design & Co-design of Embedded Systems10 Example: 3-state buffer SC_MODULE(tristate_buf){ sc_in input; sc_out output; sc_in enable; void process() { sc_bit in, en; sc_logic out; in=input; en=enable; // reading inputs to temporary variables if(en) out = in; else out = 'z'; output = out;// writing a temporary variable to output } SC_CTOR(tristate_buf) { SC_METHOD(process); sensitive<<enable<<input; } };
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2005 Design & Co-design of Embedded Systems11 Integer Types: Fixed Precision zFixed Precision Unsigned and Signed Integers yInteger variables with fixed width (number of bits) ysc_int, sc_uint x1<= n <=64 ySigned representation uses 2’s complement yUnderlying implementation: 64 bit integer x-D_32BIT_ compiler directive Can freely be mixed with C++ integers ( int, short, long )
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2005 Design & Co-design of Embedded Systems12 Fixed Precision Integers (cont’d) zDefined operators yBitwise~&|^>><< yArithemtic+-*/% yAssignment+=-=*=/=%= &=|=^== yEquality==!= yRelational >= yAuto-inc/dec++-- yBit Select[] yPart Select.range(,) yConcatenation(,)
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2005 Design & Co-design of Embedded Systems13 Fixed Precision Integers (cont’d) zExamples: sc_logic mybit; sc_uint myuint; mybit = myuint[7]; sc_uint myrange; myrange = myuint.range(5,2); sc_uint my12int; my12int = (myuint, myrange);
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2005 Design & Co-design of Embedded Systems14 Fixed Precision Integers (cont’d) sc_uint u1, u2; sc_int i1, i2; u1 = i1;// convert int to uint i2 = u2;// convert uint to int // BUG! in SystemC 2.0 User’s Guide
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2005 Design & Co-design of Embedded Systems15 Integer Types: Arbitrary Precision Integers zIntegers with (virtually) no width limit yMAX_NBITSdefined in sc_constants.h ysc_bigint, sc_biguint ySigned representation uses 2’s complement Operators are the same as sc_int, sc_uint Can be intermixed with sc_int, sc_uint, and C++ integer types
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2005 Design & Co-design of Embedded Systems16 Bit-Vector Types: Arbitrary Length Bit Vector zArbitrary Length Bit Vector yVector of 2-valued bits ysc_bv yNo arithmetic operation yAssignment: String of ‘0’ and ‘1’ chars yReduction operations and_reduce(), nand, or, nor, xor, xnor sc_bv databus; databus = “100100”; sc_logic result; result = databus.or_reduce();
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2005 Design & Co-design of Embedded Systems17 Arbitrary Length Bit Vector (cont’d) zDefined operators yBitwise~&|^>><< yAssignment=&=|=^= yEquality==!= yBit Select[] yPart Select.range(,) yConcatenation(,) yReductionand_reduce()or_reduce() xor_reduce()
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2005 Design & Co-design of Embedded Systems18 Arbitrary Length Bit Vector (cont’d) zExamples: sc_bv data16; sc_bv data32; data32.range(15,0) = data16; data16 = (data32.range(7,0), data32.range(23,16)); (data16.range(3,0),data16.range(15,12)) = data32.range(7,0); sc_bit y; sc_bv x; y = x[6]; sc_bv x; sc_bv y; y = x.range(0,7);
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2005 Design & Co-design of Embedded Systems19 Arbitrary Length Bit Vector (cont’d) zArithmetic operations not directly supported sc_bv b8=“11001010”; sc_uint u8; u8=b8; u8+=5; // or any other arithmetic b8=u8;
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2005 Design & Co-design of Embedded Systems20 Bit-Vector Types: Arbitrary Length Logic Vector zArbitrary Length Logic Vector yVector of 4-valued bits ysc_lv yNo arithmetic operation xAny ‘x’ or ‘z’ in the RHS: runtime warning + undefined result yAssignment: String of ‘0’, ‘1’, ‘x’, ‘z’ chars Operators are the same as sc_bv
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2005 Design & Co-design of Embedded Systems21 Arbitrary Length Logic Vector (cont’d) zExample: sc_lv bus1; if(enable) bus1 = “01xz10xx”; else bus1 = “zzzzzzzz”; cout<<bus1.to_string(); // OR: cout<<bus1
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2005 Design & Co-design of Embedded Systems22 Example: A Memory Module #define DATA_WIDTH 8 #define ADDR_WIDTH 4 SC_MODULE(memory) { sc_in chipEnable; sc_in readWrite; sc_inout > dataBus; sc_in > addrBus; sc_uint memArray[2^ADDR_WIDTH]; void process() { if ( chipEnable.read()=='0') { dataBus.write( "zzzzzzzz" ); return; } sc_lv addr_lv = addrBus.read(); sc_uint addr = addr_lv; if (readWrite.read()=='1') dataBus.write( memArray[addr] ); else memArray[addr]=dataBus.read(); } SC_CTOR(memory) { SC_METHOD(process); sensitive<<chipEnable<<readWrite<<dataBus; // Also: initialize memArray to zero } };
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2005 Design & Co-design of Embedded Systems23 Fixed-Point Types zUsage yHW implementation of Floating-point arithmetic MantissaSExponent Floating point representation (2’s complement) binary value Fixed point representation
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2005 Design & Co-design of Embedded Systems24 Fixed-Point Types (cont’d) zAdvantages yLess area yMore speed zDisadvantages yNarrower representable range of numbers yUniform resolution over entire range zProblems to be addressed yOverflow yQuantization zTo Be Discussed in Next Session
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Data Types in SystemC Complementary Issues Regarding Data Types
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2005 Design & Co-design of Embedded Systems26 Complementary Issues zSimulation Speed Issues zUser Defined Type Issues yEquality-check Operator yTracing a User-Defined Type
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2005 Design & Co-design of Embedded Systems27 Speed Issues: Integer Types sc_bigint sc_biguint sc_int sc_uint C++ Types sc_int sc_uint with -D_32BIT_ with MAX_NBITS not defined with MAX_NBITS defined
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2005 Design & Co-design of Embedded Systems28 Speed Issues: Bit and Logic Types sc_logic sc_bit sc_lvsc_bv
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2005 Design & Co-design of Embedded Systems29 User-Defined Type Issues zRequired for every type used as signal or port 1.Equality-Check Operator struct packet_type { int info, seq, retry; bool operator == (const packet_type& rhs) const { return (rhs.info == info && rhs.seq == seq && rhs.retry == retry); } }; write() new_val==old_val
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2005 Design & Co-design of Embedded Systems30 User-Defined Type Issues (cont’d) 2.A special trace function void sc_trace(sc_trace_file *tf, const packet_type& v, const sc_string& NAME) { sc_trace(tf, v.info, NAME + ".info"); sc_trace(tf, v.seq, NAME + ".seq"); sc_trace(tf, v.retry, NAME + ".retry"); }
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2005 Design & Co-design of Embedded Systems31 User-Defined Type Issues (cont’d) 3.A special streaming operator ostream & operator <<(ostream &os, packet_type p) { os << p.info << p.seq << p.retry << endl; return os; }
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2005 Design & Co-design of Embedded Systems32 What we learned today zHardware-centric data types in SystemC zUser-Defined Data Types yRequired operator yTracing Issues
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