1. A Unified Approach to Design Distributed Amplifiers Rasit Onur Topaloglu PhD. Student rtopalog@cse.ucsd.edu

2. Limitations with Classical Amplifiers G.BW  gm/C Combining amplifiers in parallel does not help as it also increases the total C Gain-bandwidth product is proportional to transconductance over capacitance High Gain-bandwidth product is the aim in amplifier design

3. Tying Amplifier to Device Physics These capacitances can be incorporated in or counted as capacitors in a transmission line Input and output have capacitive impedances CgsCds G S D

4. Basic Transmission Line A low-pass transmission line can easily be constructed of inductors and capacitors..

5. Principle of Distributed Amplification.. Couple two transmission lines by amplifiers.. RFin RFout

6. Termination of Unwanted Waves.. There will be forward and backward propagating waves at nodes RFin RFout Terminate unwanted ones using a load on both lines

7. Exploitation of Amplifier Capacitances.. Input and output capacitances of an amplifier can be used to replace capacitors RFin RFout Even a single transistor amplifier satisfactory gate line drain line

8. Design Considerations for Transmission Lines Each lines designed to have a cut-off frequency larger than targeted operation frequency of amplifier by a safe margin f c =1/(  LC) Z o = L/C

9. m-derived Sections for a Better Matching LC sections (constant-k transmission lines) matched to load using an m-derived section to provide constant Z over a wider range m=0.6 is identified as a practical rule of thumb value

10. m-derived vs. Constant-k Low- pass T-section m=1 corresponds to constant-k

11. m-derived vs. Constant-k Line Z over Frequency m=1 corresponds to constant-k

12. Phase Matching of Lines Cgs~4Cds for a transistor If L chosen to be constant, C matching required on gate and drain lines for a better amplifier response Either add additional C in parallel with drain to increase it=> provides higher BW Or add additional C in series with gate to reduce it=> provides higher gain

13. Staggering to Avoid Gain Peak near Cut-off Staggering is introducing a deliberate mismatch between gate and drain lines to avoid a peak near line cut-off frequency Drain line cut-off chosen as ~0.7 times gate line cut-off

14. Number of Sections Increasing number of sections increases gain linearly as opposed to quadratic increase in cascade amplifiers Line losses and parasitics prevent an infinite increase Optimal number of stages can be explored analytically or by simulation A g =1/4 x (R g  2 C in 2 Z o ) n og =1/2 x A g [A monolithic GaAs 1-13GHz traveling wave amplifier, Y. Ayasli, et. al.]

15. Design Example [SOI CMOS Traveling Wave Amplifier with NF below 3.8 dB from 0.1-40 GHz, F. Ellinger]

16. Design Example

20. SOI CMOS Noise Figure and Gain

21. PHEMT Noise Figure and Gain Technology Comparison SOI CMOS 90nm, 17mA, 2V Cgs=0.06pF Cds=0.015pF PHEMT 40mA, 2V Cgs=0.27pF Cds=0.030pF Higher capacitance values makes possible to use smaller inductors for same cut-off frequency Lossy Inductor Model: Inductor Q assumed 20 @ 1GHz with a parasitic series resistor of 10  and Q being directly proportional to frequency

22. Design Considerations for PHEMT Cds used to decrease the high ratio difference between Cgs and Cds; thereby obtaining a gain with less ripple. Compromising high frequency gain, a smoother response is obtained Usage of series Cgs would deteriorate low frequency response Same inductor value used for both gate and drain lines

23. PHEMT Gain&Noise Optimization Goals are set for gain and noise Random optimization used Only inductor used for the optimization value; thereby keeping system specific termination and source resistors intact

24. PHEMT Optimization Results With some sacrifice in gain ripple, noise figure has been significantly improved and circuit operates up to 47GHz After optimization

25. Usage of Transmission Lines Using Richard’s transformation, inductors can be replaced by transmission lines. Choosing an electrical length of 45  and a reference cut-off frequency equal to the gate line, optimization gave a Zo of 30.6 and an operation range of up to 57 GHz for noise considerations After optimization

26. Conclusions Distributed amplifiers, an ancient field of study, will continue evolving as a good field to work in Broadband techniques will not be able to outdo distributed amplifiers 60GHz low noise amplifiers for optical circuits are almost here

27. Design Plan Given gain and bandwidth considerations, Identify pick f c and Z o for gate line to find Lg and Using staggering with 0.7 f c =1/(  LC) Z o = L/C L d =(1/0.7)L g C d =(1/0.7)C g Find shunt capacitance to get C d from device model

28. Design Plan Identify device size using C g Using staggering with 0.7 L d =(1/0.7)L g C d =(1/0.7)C g Find shunt capacitance to get C d from device model WL= C g /C ox