1. Electrical and Computer Engineering University of Cyprus 22-10-2014 LAB3: IMPROVING MIPS PERFORMANCE WITH PIPELINING

2. Previous Labs: MIPS single-cycle with Memory System 2

3. In this Lab: Pipelining You are expected to:  Understand the concept  Be familiar with the 5 MIPS pipeline stages  Understand the three pipeline hazards and their solutions. 3

4. PIPELINING Technique in which the execution of several instructions is overlapped. Each instruction is broken into several stages. Stages can operate concurrently PROVIDED WE HAVE SEPARATE RESOURCES FOR EACH STAGE! => each step uses a different functional unit. Note: execution time for a single instruction is NOT improved. Throughput of several instructions is improved. 4

5. Major Pipeline Benefit = Performance Ideal Performance  Time/instruction = non-piped-time/#stages  This is an asymptote of course, but +10% is commonly achieved Two ways to view the performance mechanism Reduced CPI (i.e. non-piped to piped change)  Close to 1 instruction/cycle if you’re lucky Reduced cycle-time (i.e. increasing pipeline depth)  Work split into more stages  Simpler stages result in faster clock cycles 5

6. Other Pipeline Benefits Completely hardware mechanism All modern machines are pipelined  This was the key technique to advancing performance in the 80’s  In the 90’s the move was to multiple pipelines Beware, no benefit is totally free/good 6

7. 7 Laundry analogy to pipelining

8. Implementation of a RISC (Unpipelined, Multicycle) Implementation of an integer subset of a RISC architecture that takes at most 5 clock cycles.  Instruction Fetch (IF)  Instruction Decode/Register Fetch (ID)  Execution/Effective Address Calculation (EX)  Memory Access (MEM)  Write-Back (WB) 8

9. Review: Single-cycle Datapath for MIPS Data Memory (Dmem) PCRegisters ALU Instruction Memory (Imem) Stage 1Stage 2Stage 3 Stage 4 Stage 5 IFtchDcdExecMemWB Use datapath figure to represent pipeline ALU IM Reg DMReg 9

10. Classic 5 Stage Pipeline for a RISC Processor 10

11. Pipelined Execution Representation To simplify pipeline, every instruction takes same number of steps, called stages One clock cycle per stage IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB Program Flow Time 11

12. Important Pipeline Characteristics Latency Latency  Time it takes an instruction to go through the pipe  Latency = # stages * stage-delay  Dominant feature if there are a lot of exceptions… Throughput Throughput  Determined by the rate at which instructions can start/finish  Dominant feature if there are few exceptions 12

13. Pipelining Lessons Pipelining doesn’t help latency (execution time) of single task, it helps throughput of entire workload Multiple tasks operating simultaneously using different resources Potential speedup = Number of pipe stages Time to “fill” pipeline and time to “drain” it reduces speedup Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipe stages also reduces speedup 13

14. Single Cycle Datapath Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem 4 PCPC addadd addadd << 2 MuxMux PCSrc ALUOp ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0 14

15. Required Changes to Datapath Introduce registers to separate 5 stages by putting IF/ID, ID/EX, EX/MEM, and MEM/WB registers in the datapath. Next PC value is computed in the 3 rd step, but we need to bring in next instruction in the next cycle. Branch address is computed in 3 rd stage. With pipeline, the PC value has changed! Must carry the PC value along with instruction. 15

16. Changes to Datapath (cont.) For lw instruction, we need write register address at stage 5. But the IR is now occupied by another instruction! So, we must carry the IR destination field as we move along the stages. See connection in fig. 16

17. Pipelined Datapath (with Pipeline Regs) Address 4 32 0 Add Add result Shift left 2 I n s t r u c t i o n M u x 0 1 Add PC 0 Address Write data M u x 1 Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero Imem Dmem Regs IF/ID ID/EX EX/MEM MEM/WB 64 bits 133 bits 102 bits 69 bits 5 Fetch Decode Execute Memory Write Back 17

18. Pipelined Datapath (with Control Signals) 18

19. Control for Pipelined Datapath RegDst ALUOp[1:0] ALUSrc MemRead MemWrite Branch RegWrite MemtoReg  Basic approach: build on single-cycle control  Place control unit in ID stage  Pass control signals to following stages 19

20. Control for Pipelined Datapath 20

21. Datapath and Control Unit 21

22. Tracking Control Signals - Cycle 1 LW 22

23. Tracking Control Signals - Cycle 2 SWLW 23

24. Tracking Control Signals - Cycle 3 ADDSWLW 0 01 1 24

25. Tracking Control Signals - Cycle 4 SUBADD SW LW 1 0 0 25

26. 1 1 ADD Tracking Control Signals - Cycle 5 SUB SW LW 26

27. Can pipelining get us into trouble? Yes: Pipeline Hazards Hazards occur because data required for executing the current instruction may not be available.  Structural hazards: attempt to use the same resource two different ways at the same time  Control hazards: attempt to make a decision before condition is evaluated branch instructions interrupts 27

28. Pipelining troubles (cont.) Data hazards occur when an instruction needs register contents for an arithmetic/ logical/memory instruction, before they are ready.  instruction depends on result of prior instruction still in the pipeline Can always resolve hazards by waiting:  pipeline control must detect the hazard  take action (or delay action) to resolve hazards 28

29. Hazard detection & Forwarding Units 29

30. Forwarding: A solution to Data Hazards 30

31. Stalls Forwarding will not always solve the problems of data hazards. For example, suppose an add instruction follows a load word (lw), and the add involves the register that receives the memory data. In this case, forwarding will not work. The reason is that the data must be read from memory, and so it will not be available until the end of the MEM cycle. Thus the required data is not available for a forward, and the add instruction. if it proceeds, will process the wrong data. A solution to this problem is the stall. A stall halts the instruction awaiting data, while the key instruction (a lw in this case) proceeds to the end of the MEM cycle, after which the desired data is available to the add. 31

32. Other Problems With Branches A remaining problem is what to do about instructions following a branch. Even assuming forwarding and stalls, the branch/no branch decision is not made until the third stage. This means that in the MIPS pipeline, two following instructions will enter the pipe before the branch/no branch decision is made. What if:  The following instructions were for the case of “branch taken” and the branch was not taken.  The following instructions were for “branch not taken” and it was taken. In either case, the wrong instructions are in the pipe and they must be eliminated (“flushed”). How can this problem be prevented? 32

33. Control Hazard Approach One approach is to always assume the branch is(or is not) taken: Say we assume the branch is never taken. Then if the instruction in ALU/EX is a branch, the instructions in IF and ID/RF will be those in the “not taken” program line (branch determination is made in ALU/EX).  It this assumption is correct, the pipeline will continue to flow without delay.  When the branch is taken, instructions in IF and ID/RF must be “flushed,” usually by changing the “op” code of those instructions to a “nop” and letting them proceed to the end of the pipe. 33

34. Summary Pipelining is a fundamental concept in computers/nature  Multiple instructions in flight  Limited by length of longest stage  Latency vs.Throughput Hazards gum up the works 34