1. 1 CSE370, Lecture 10 Lecture 10 u Logistics n HW3 due Friday (cover materials up to this lecture) n Lab3 going on this week n Midterm 1: a week from today --- material up to this lecture u Last lecture n Don’t cares n POS minimization with K-map n K-maps design examples u Today n "Switching-network" logic blocks (multiplexers/demultiplexers)

2. 2 CSE370, Lecture 10 Switching-network logic blocks u Multiplexer (MUX) n Routes one of many inputs to a single output n Also called a selector u Demultiplexer (DEMUX) n Routes a single input to one of many outputs n Also called a decoder multiplexerdemultiplexer control We construct these devices from: logic gates networks of tran- sistor switches

3. 3 CSE370, Lecture 10 The “WHY” slide u Multiplexers/Demultiplexers n If you had the ability to select which input to operate, the same part of a circuit can be used multiple times. So if you have a lot of inputs and all of them are supposed to go through same complex logic functions, you can save a lot of space on your circuit board by using a multiplexer. n Then you will also need a demultiplexer to decode the output coming out in serial into separate output ports.

4. 4 CSE370, Lecture 10 “WHY”: Sharing complex logic functions u Share an adder: Select inputs; route sum multiple inputs multiple output destinations MUX A B Sum A0A1A0A1 SsSs SbSb B0B1B0B1 MUX DEMUX Z 0 Z 1 single adder SaSa

5. 5 CSE370, Lecture 10 Multiplexers u Basic concept n 2 n data inputs; n control inputs ("selects"); 1 output n Connects one of 2 n inputs to the output n “Selects” decide which input connects to output n Two alternative truth-tables: Functional and Logical Example: A 2:1 Mux Z = SIn 1 + S'In o Functional truth table SZ 0In 0 1In 1 In 1 In 0 SZ 0000 0010 0101 0110 1000 1011 1101 1111 Logical truth table I0I0 S I1I1 Z

6. 6 CSE370, Lecture 10 Multiplexers (con't) u 2:1 mux:Z = S'In 0 + SIn 1 u 4:1 mux:Z = S 0 'S 1 'In 0 + S 0 'S 1 In 1 + S 0 S 1 'In 2 + S 0 S 1 In 3 u 8:1 mux:Z = S 0 'S 1 'S 2 'In 0 + S 0 'S 1 S 2 In 1 +... I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 S 0 S 1 S 2 8:1 mux Z I0I1I2I3I0I1I2I3 S 0 S 1 4:1 mux Z I0I1I0I1 S0S0 2:1 mux Z

7. 7 CSE370, Lecture 10 Logic-gate implementation of multiplexers 2:1 mux4:1 mux I0I1I2I3I0I1I2I3 S 0 S 1 I0I0 S I1I1 Z Z Z

8. 8 CSE370, Lecture 10 Cascading multiplexers u Can form large multiplexers from smaller ones n Many implementation options Z 4:1 mux S2S2 2:1 mux I4I5I6I7I4I5I6I7 S 0 S 1 4:1 mux S0S0 Z S 1 S 2 4:1 mux 2:1 mux I4I5I4I5 I2I3I2I3 I0I1I0I1 I6I7I6I7 8:1 mux I0I1I2I3I0I1I2I3

9. 9 CSE370, Lecture 10 Multiplexers as general-purpose logic u A 2 n :1 mux can implement any function of n variables n A lookup table n A 2 n – 1 :1 mux also can implement any function of n variables u Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB(0) + AB(1) ABCF00010010010101101000101011011111ABCF00010010010101101000101011011111 C' C' 0 1 S1S0 F 01230123 4:1 MUX C' C' 0 1 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 F A B C A B

10. 10 CSE370, Lecture 10 Multiplexers as general-purpose logic u Implementing a 2 n-1 :1 mux as a function of n variables n (n-1) mux control variables S 0 – S n–1 n One data variable S n n Four possible values for each data input: 0, 1, S n, S n ' n Example: F(A,B,C,D) implemented using an 8:1 mux Choose A,B,C as control variables Choose D as a data variable 0123456701234567 1 D 0 1 D' D D' D' A 8:1 MUX B C F D 10111000110101101011100011010110 AB CD A 00011110 00 01 11 10 C B S2 S1 S0

11. 11 CSE370, Lecture 10 Demultiplexers (DEMUX) u Basic concept n Single data input; n control inputs (“selects”); 2 n outputs n Single input connects to one of 2 n outputs n “Selects” decide which output is connected to the input n When used as a decoder, the input is called an “enable” (G) 1:2 Decoder: Out0 = G  S' Out1 = G  S 2:4 Decoder: Out0 = G  S1'  S0' Out1 = G  S1'  S0 Out2 = G  S1  S0' Out3 = G  S1  S0 3:8 Decoder: Out0 = G  S2'  S1'  S0' Out1 = G  S2'  S1'  S0 Out2 = G  S2'  S1  S0' Out3 = G  S2'  S1  S0 Out4 = G  S2  S1'  S0' Out5 = G  S2  S1'  S0 Out6 = G  S2  S1  S0' Out7 = G  S2  S1  S0

12. 12 CSE370, Lecture 10 Logic-gate implementation of demultiplexers 1:2 demux Out 0 G S Out 1 2:4 demux

13. 13 CSE370, Lecture 10 Demultiplexers as general-purpose logic u A n:2 n demux can implement any function of n variables n DEMUX as logic building block n Use variables as select inputs n Tie enable input to logic 1 n Sum the appropriate minterms (extra OR gate) demultiplexer “decodes” appropriate minterms from the control signals C AB 0A'B'C' 1A'B'C 2A'BC' 3A'BC 4AB'C' 5AB'C 6ABC' 7ABC S2 3:8 Demux S1S0 1

14. 14 CSE370, Lecture 10 Demultiplexers as general-purpose logic Example F1 = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A'+B'+C'+D') AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 Demux Enable = 1 CD F1 F2 F3

15. 15 CSE370, Lecture 10 Cascading demultiplexers u 5:32 demux 0 A'B'C'D'E' 1 2 3 4 5 6 7 S2 3:8 Demux S1S0 AB 01230123 S1 2:4 Demux S0 F E CD 0 1 2 3 4 5 6 7 ABCDE S2S1S0 0 1 2 A'BC'DE' 3 4 5 6 7 S2S1S0 E CD 0 AB'C'D'E' 1 2 3 4 5 6 7 AB'CDE S2S1S0 3:8 Demux 3:8 Demux 3:8 Demux

16. 16 CSE370, Lecture 10 inputs outputs product terms AND array OR array Programmable logic (PLAs & PALs ) u Concept: Large array of uncommitted AND/OR gates n Actually NAND/NOR gates n You program the array by making or breaking connections íProgrammable block for sum-of-products logic

17. 17 CSE370, Lecture 10 All two-level logic functions are available u You "program" the wire connections A 3-input, 5-term, 4-function PLA