1. DEC Alpha Course : CS 420 Student : Narith Kun Instructor : Dr. Chi-cheng Lin Date : April 26, 2010

2. History Alpha was born out of an earlier RISC project named PRISM but it was cancelled. The decision was also made to upgrade the design to a full 64-bit implementation from PRISM's 32-bit, a conversion all of the major RISC vendors were undertaking The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek.

3. Instruction Set Architecture The Alpha Approach to RISC Architecture Alpha is a 64-bit architecture that is designed with particular emphasis on the three elements that most affect performance: clock speed, multiple instruction issue, and multiple processors.

4. What is ISA (alpha DEC) Aspects of the computer visible to the programmer: Data Types Registers Instruction format Addressing

5. Data format Alpha is a load/store RISC architecture with the following data characteristics: All operations are done between 64-bit registers. Memory is accessed via 64-bit virtual byte addresses, using the little- endian or, optionally, the big-endian byte numbering convention. There are 32 integer registers and 32 floating-point registers. Longword (32-bit) and quadword (64-bit) integers are supported. Five floating-point data types are supported: – VAX F_floating (32-bit) – VAX G_floating (64-bit) – IEEE single (32-bit) – IEEE double (64-bit) – IEEE extended (128-bit)

6. Instruction commone

7. Instruction

8. Instruction Format 31-2625-2120-1615-54-0 Op codeNumberPAL format Op codeRADispBranch format Op codeRARBDispMemory format Op codeRARBFunctionRCOperate format Op codeFAFBFunctionFCFloating Op

9. Instruction format PAL code (Privileged Architecture Library) use to specify extended processor function. It specify in the function code field, one of a few dozen complex Conditional branch instructions test register Ra and specify a signed 21-bit PC-relative longword target displacement. Subroutine calls put the return address in register Ra. Load and store instructions move bytes, words, longwords, or quadwords between register Ra and memory, using Rb plus a signed 16-bit displacement as the memory address.

10. Instruction Format 31-2625-2120-1615-131211-54-0 Op codeRaRbSBZ0FunctionRc Op codeRaLit1FunctionRc

11. Instruction format Operate instructions for floating-point and integer operations -Word and byte sign-extension operators. -Floating-point operations use Ra and Rb as source registers and write the result in register Rc. There is an 11-bit extended opcode in the function field. - Integer operations use Ra and Rb or an 8-bit literal as the source operand, and write the result in register Rc. -Integer operate instructions can use the Rb field and part of the function field to specify an 8-bit literal. There is a 7-bit extended op code in the function field.

12. Operand Notation Ra An integer register operand in the Ra field of the instruction Rb An integer register operand in the Rb field of the instruction #b An integer literal operand in the Rb field of the instruction Rc An integer register operand in the Rc field of the instruction Fa A floating-point register operand in the Ra field of the instruction Fb A floating-point register operand in the Rb field of the instruction Fc A floating-point register operand in the Rc field of the instruction

13. Load Address Format: LDAx Ra.wq, disp.ab (Rb.ab) !Memory format Operation: Ra  Rbv + SEXT(disp) !LDA Ra  Rbv + SEXT(disp*65536) (sign extension) !LDAH Exceptions: None Instruction mnemonics: LDA Load Address LDAH Load Address High Qualifiers: None Description: The virtual address is computed by adding register Rb to the sign extended 16-bit displacement for LDA, and 65536 times the sign- extended 16-bit displacement for LDAH. The 64-bit result is written to register Ra.

14. Addressing Mode Register direct Immediate Register indirect with displacement PC-relative Operands in the Alpha can be 1, 2, 4 or 8 bytes in length.

15. Processor Design Alpha 21264:

16. Pipelining Stages DEC Alpha 21264: 9 stages pipeline Address translat e and cache access Decode instruct ion and read register Executi on Address translat e and cache access Tag check Write register file Write Memor y

17. Data path

18. 01 2 3 45 Bran prediction Instruction Cache I resister rename map FP resister rename map I issue Que ue I issue Que ue Fp issue Que ue Fp issue Que ue I regis ter File I regis ter File FP regis ter File FP regis ter File ALU Shifter ALU Shifter ALU Shifter Mutiplier ALU Shifter Mutiplier F-Add, divide, square root F- Multiply Data Cache

19. Conclusion Design Policies Design Principle 1: Simplicity favors regularity 32 register Design Principle 2: Smaller is faster Design Principle 3: Make the common case fast Immediate operand avoids a load instruction Design Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible Bi-endian

20. Conclusion Memory mapped file can be more difficult to implement in 32-bit architectures. A large files cannot be memory mapped easily to 32-bit architectures data encryption software can benefit greatly from 64- bit registers the same data occupies more space in memory x86-based 64-bit systems sometimes lack equivalents to software that is written for 32-bit architectures  this architecture should be more developing in the future. It is good way to deal with large data files.

21. Work cited The Alpha architecture handbook, version 4 http://www.comms.scitech.susx.ac.uk/fft/programming/a lphaahb.pdf Patterson and Hennessy.Computer Organization and Design, 4 ed, Chapter Six Pipelined Processor Pipelining http://www.csc.gatech.edu/~copeland/3055- 00/pdf/lec_04_notes.pdf