1. 80GHz Modulator Designs Ian Harrison School of Electrical and Electronic Engineering University of Nottingham UK Work done at Department of ECE University of California, Santa Barbara USA Harrison@ece.ucsb.edu 805-893-8044, 805-893-3262 fax Special thanks PK, Zak, Mattias for fabrication of circuits and devices Miguel for advice Paidi and Navin for cricket discussions Mark Rodwell for useful discussion and use of infrastructure

2. Introduction Concentrate on more recent work Thermal Modelling Modulator work –design issues –Simulation results

3. Design Specifications Two types of optical modulator –LiNb0 3 Mach Zehnder -Interference Split beam into 2, induce 0 or 180 phase shift Large driving voltage eg 10GBits 5Vpp –Electroabsorption Quantum confined stark effect Smaller driving voltage eg 10GBits 3Vpp Design specifications E=0E≠0 E=0 E≠0 λ Attn EA modulator 2V, 50 Ohm input Output should be matched

4. Switching speed limited by output capacitance How do we get speed improvement Design Specifications set ΔV and R L  sets I Reduce C by decreasing A C  Increase in J since I fixed  J limited by Kirk Effect  Increase in J increase dissipated power density Formula simplistic  insight

5. Kirk effect and switching time Above J kirk massive increase in base charge  Base push out (Field Screening) V sat =3.5 10 5 cms -1  Wide emitter, narrow base mesa R b limits the emitter width  V CE Predicts straight line

6. Why is thermal management important? As J increases so does the power density. This will lead to an increase in the temperature. TCTC J Kirk LeLe ÅmAμm -2 μm 30001.081 20002.334 15004.119 10009.88.6 For V CE =1V  P D =10.6mWμm -3 For V CE =1V  P D =98mWμm -3 !!

7. Thermal Modeling of HBT (1) 3D Finite Element using Ansys 5.7 K (Thermal conductivity) depends temperature K depends on doping For GaAs heavily doped GaAs 65% less than undoped GaAs Unknown for InP or InGaAs use GaAs dependency J.C.Brice in “Properties of Indium phosphide” eds S Adachi and J.Brice pubs INSPEC London p20-21 S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p34-39 “CRC Materials science and engineering handbook”, 2nd edition,eds J.F Shackelford,A.Alexander, and J.S Park, pubs CRC press, Boca Raton, p270 MaterialK 300 nK 300 (exp)Refs InP0.681.420.68-0.8771 InGaAs0.0481.3750.048-0.0612 Au3.17-3  Large uncertainty in values

8. Layout used for simulation validation Layer structure Emitter0.04μm n+ InGaAs 0.12 μm n- InP Base0.03 μm p+ InGaAs Collector Setback Grade Drift 0.02 μm InGaAs 0.024 μm Grade 0.156 μm InP Subcollector Etchstop0.050 μm n+ InGaAs 0.200 μm n+ InP Substrate500 μm Fe: InP Need simplified model for simulation  reduce simulation time and storage requirements Ignore base pad collector interconnect 2 orthogonal symmetry lines Simulate only ¼ device Polyimide for passivation Very low K ignore In thermal analysis After M. Dahlstrom Actual device Simulated ¼ Device

9. Validation of Model Caused by Low K of InGaAs Max T in Collector Ave Tj (Base-Emitter) =26.20°C Measured Tj=26°C Good agreement. Advice Limit InGaAs Increase size of emitter arm

10. Effect of decreasing collector thickness Choose Le For J=J Kirk We=0.5um 50% duty cycle Assumptions Devices thermally isolated Device structure identical to validation structure Perfect switching waveform Observations Temperature increases rapidly for thin collectors (ΔT max =60°C for T C =1000Å) Collector temperature always higher than T j (ΔTMax-ΔTj)>30°C ) Increase in I SC  possible failure mechanism ( Major failure problem in GaAs HBT’s) Temperature of one device approximately double when circuit is not switching

11. Analysis of 40,80,160 Gbit/s devices To obtain speed inprovements require to scale other device parameters. Speed(Gbit/s)4080160 Collector Thickness(Å)300020001000 Base Sheet resistance ()() 750700 Base contact resistance (-m2)(-m2) 1502010 Base Thickness(Å)400300250 Base Mesa width (  m) 31.60.4 Current Density (mA/  m 2 ) 12.39.8 Emitter. Junction Width (  m) 10.80.2 Emitter Parasitic resistivity (-m2)(-m2) 50205 Emitter Length (  m) 63.33.2 Predicted MS-DFF(GHz)62125237 FtFt (GHz)170260500 F max (GHz)1704401000 TjTj (K)7.51428 T Max (K)102049 T Max (No Etch Stop layer)(K)7.51321 Conservative 1.5x bit rate Reduction of parasitic C BC Device parameters after Rodwell et al When not switching values will double

12. Thermal Analysis using ADS For simulations need a model that can be solved by ADS so that thermal and circuit simulations can be coupled. Thermal generation  current source Thermal resistance  resistors Thermal capacity  capacitors (If static not needed) Temperature variation of thermal conductivity not modelled because resistors do not depend on current (This restriction could be lifted) R network easily solved Using ADS

13. Coupled Circuit-Thermal modelling How do the advance device models do it? –Device at one temperature –Devices thermally isolated and described by a single resistance –Thermal circuit hidden from user How do we want to do it –Access to thermal circuit –β only slightly temperature dependent –Large change in V BE(ON) Temperate rise Value used in model Ambient T Power dissipated in the device Thermal Resistance Β is the band gap shrinkage factor Not usually given but optical measurements on band gap ( Optical values must be used with caution ) 0.0004 for both InP and InGaAs My model

14. Can we measure R th (Method of Lui et al ) Ramp I B for different V CE Measure V BE and I C Depends on current density Large uncertainty in values. Fitting regression curves helps to reduce error

15. An alternative method for finding R T I C fixed, sweep V B From gradient  R T Obtain R T (Pave) Changes in V C larger more accurate RT measured at lower Pave  Thermal instability possible  Need to be careful on the V B range Ic= 6mA,6mA Ic=12mA,12mA Ic= 6mA,6mA Ic=12mA,12mA

16. Comparison of the two methods Classic Method Linear interpolation. Empirical Curve fit “New method”  Classic method badly affected by the 4145 resolution. Better measurements at very high power. Often leads to device failures Problems with every fourth measurement of 4145 in “new” method Need to compare the two methods using the 4155 Emitter Mask 12 x 0.7 mesa width 1.7

17. Which model to estimate R th Finite elements clearly shows diffusion of heat along the collector under the base contacts. R th should depend on base mesa size Model 1 Models flow of heat under base  Thermal circuit complex Model 2 Thermal circuit simple  Over estimates R T Both Models  Both will underestimate R T at high powers Experimental results RT(C/W)1.72.12.7 4550051006200 121800 Mesa Width Length  Use Model 2 Model 1 Model 2

18. Thermal resistance calculations Thermal resistance of layers can be estimated from the thermal conductivity if no heat spreading is assumed. The emitter interconnect acts as a thermal link The thermal resistance of the substrate is estimate by solving the 3D heat flow problem using separable variables technique. This is the same method Lui et al used to calculate RT of single and multi- finger HBT power transistors.† After M. Dahlstrom RT(C/W)1.72.12.7Theory 45500510062005700 121800 2071 Mesa Width Length Spreadsheet: ThermalCalc.xls

19. Stability of single BJT’s (Intro) Well known problem solved by ballasting with emitter or base resistance. Known to be a problem in power amplifiers. May argue, incorrectly, that in digital circuits this is not a problem because we are driving the circuits with a constant current source. Need to know how large we can make the emitters before “hot spots” form and current “hogging” becomes an issue. If the transistor base is being driven with a constant voltage. The collector current will increase until it gets to point X. Any further increase in base voltage will cause an infinite increase in the collector current resulting in physical damage to the device. X

20. Single Emitter Stability Caused by the increase in RT when device size is reduced. Caused by the reduction of Re with length Uncertainty in Re ρ E= 60Ω from DC measurements J =1  5mAμm -2 Optimum operating point

21. Hot spot formation (not finished) Device broken into sections Thermal model of substrate Base electrical resistance Thermal resistance of the emitter connection Need to do 1.Simulate DC measurements 2.Compare with measurements

22. Modulator design (Matching) Passive Resistive FeedbackFeedback Passive simple  high bias current All active circuits Bias current lower  need to prevent saturation Resistive feedback  No flexibility Z o =1/g m Feedback Z o =1/(g m β) but additional EF more ringing RCRC Feedback β<1

23. Effect of current source design on output Capacitive coupling to Control line reduces output resistance Common Reference Different Reference Vo Vm Vi Current switch (only one half) Use resistor:- inefficient power use, but simple

24. Output stage options Miller effect increases output cap Performance depends on the quality of the ground Bias generated by diode With diode baseIdeal Vsrc

25. Current designs 2 and 3 stage amplifiers Cascode and simple output 3 stage cascode output 80GBit/s 160GBit/s Simulations show that 160GBit is just possible with 1500A collector.

26. What to do in the future Fabricate and test the current design Design amplifiers with output voltage Simulate with self heating Investigate the more advanced BJT models

27. Conclusion 160 Gbits Modulator has been designed Electro -thermal model has been developed which can be simulated using ADS What would I change if I could rewind the clock Gone in the clean room.