1. 1 Hardware Description Languages: a Comparison of AHPL and VHDL By Tamas Kasza AHPL&VHDL Digital System Design 1 (ECE 5571) Spring 2003 A presentation for

2. 2 Content Introduction Brief History of Hardware Description Languages (HDLs) The Roles and Relationship of AHPL and VHDL Main Similarities and Differences between AHPL and VHDL – a small case study Challenges and Future of HDLs – Summary and Discussion AHPL&VHDL

3. 3 Introduction HDLs – Hardware Description Languages Why are they useful? Maximum reliability with low-cost and time- effective development Design&Documentation at the same time Testing&Simulation is easy Maintenance is easy FPGAs and ASICs have become widely used Powerful design tools AHPL&VHDL

4. 4 HDLs HDLs – Hardware Description Languages Examples: ABEL: Simplified HDL Dataflow primitives, e.g., registers Can use to Program XILINX FPGA ALTERA Created by Altera Corporation Simplified dialect of HDL AHDL: Altera Hardware Description Language AHPL&VHDL

5. 5 HDLs - Examples CDL: Computer Design Language Academic language for teaching digital systems Dataflow language Non-hierarchical Contains conditional statements CONLAN: CONsensus LANguage Family of languages for describing various levels of abstraction Concurrent Hierarchical AHPL&VHDL

6. 6 HDLs - Examples IDL: Interactive Design Language Internal IBM language Originally for automatic generation of PLA structures Generalized to cover other circuits Concurrent Hierarchical CDL: Computer Design Language ISPS: Instruction Set Processor Specification Behavioral language Used to design software based on specific hardware Statement level timing control, but no gate level control AHPL&VHDL

7. 7 HDLs - Examples TEGAS: TEst Generation And Simulation Structural with behavioral extensions Hierarchical Allows detailed timing specifications IDL: Interactive Design Language TI-HDL: Texas Instruments Hardware Description Language Created at Texas Instruments Hierarchical Models synchronous and asynchronous circuits Non-extendable fixed data types AHPL&VHDL

8. 8 HDLs - Examples Verilog Essentially identical in function to VHDL No generate statement Simpler and syntactically different C-like Gateway Design Automation Co., 1983 Early de facto standard for ASIC programming ZEUS Created at General Electric Hierarchical Functional Descriptions Structural Descriptions Clock timing, but no gate delays No asynchronous circuits AHPL&VHDL

9. 9 Introduction - HDLs AHPL – A Hardware Programming Language First published in 1973 Widely used in the 70s and 80s It has been successfully tested on a broad spectrum of design problems Characteristics: Dataflow language Implicit clock Does not support asynchronous circuits Fixed data types Non-hierarchical AHPL&VHDL

10. 10 Introduction - HDLs VHDL – VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Introduced in 1980: Object was to achieve significant gains in VLSI technology by shortening the time from concept to implementation (18 months to 6 months) Need for a common descriptive and simulation language August 1985: VHDL Version 7.2 released December 1987: VHDL became IEEE Standard and in 1988 an ANSI standard September 1993: restandardization of VHDL in order to clarify and enhance the language 2001: Revised IEEE VHDL Standard AHPL&VHDL

11. 11 Case Study Problem: Develop a combinational logic unit description of a half adder. Specification: Input and output are both one bit When enable is 1(high), result gets x plus y When enable is 1(high), carry gets any carry of x plus y Outputs are zero when enable input is low AHPL&VHDL x y enable carry result Half Adder

12. 12 Case Study – AHPL AHPL&VHDL CLUNIT: HALFADD (x; y; enable) INPUTS:x; y; enable. OUTPUTS:HALFADD[2]. CTERMS:a; carry; result. BODY a = x  y; result = a  enable; carry = x  y  enable; HALFADD[0] = carry; HALFADD[1] = result; END

13. 13 Case Study – VHDL AHPL&VHDL ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END half_adder; x y enable carry result Half Adder First step: entity declaration describes the (input and output) interfaces of the component

14. 14 Case Study – VHDL AHPL&VHDL ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS; END half_adder_a;

15. 15 VHDL – Timing Behavior AHPL&VHDL ARCHITECTURE half_adder_b OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y after 10ns; carry <= x AND y after 12 ns; ELSE carry <= ‘0’ after 10ns; result <= ‘0’ after 12ns; END IF; END PROCESS; END half_adder_b;

16. 16 VHDL – Pure Logical AHPL&VHDL ARCHITECTURE half_adder_c OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_c;

17. 17 VHDL – Component Based AHPL&VHDL ARCHITECTURE half_adder_d OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); SIGNAL xor_res : BIT; -- internal signal BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_d;

18. 18 AHPL – VHDL Comparison AHPL&VHDL Feature Language type in generalClock Asynchronous support? Data types Hierarchy? AHPL Dataflow oriented, register transfer synthesis language ImplicitNoFixedNo VHDL Functional, behavioral, dataflow and structural model based Implicit or explicit YesFixedYes

19. 19 The Most Important Features AHPL&VHDL An effective HDL in the 21 st century should Be hierarchical, modularized  Complexity has been growing Contain application specific features Be conform to other widely used HDLs (mapping, remapping, etc.) Be easy to understand and maintain by engineers Contain graphical, as well as textual notation parts … What else?

20. 20 Thank You for Your Attention!