1. Datapath Design Computer Organization I 1 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Composing the Elements First-cut data path does an instruction in one clock cycle -Each datapath element can only do one function at a time -Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions

2. Datapath Design Computer Organization I 2 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens R-Type/Load/Store Datapath How would this execute: add $s0, $s1, $s2; 10000000000100001001010001000000 functshamtrdrtrsop

3. Datapath Design Computer Organization I 3 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens R-Type Execution 10000000000100000001110001000000 functshamtrdrtrsop Reg #s for $s1 and $s2 are input to the register file's read register ports. Low 16 bits from instruction are fed to the Sign-extend logic… irrelevant. Values from $s1 and $s2 are fetched and passed to ALU (ALUSrc set to 0 by Control).

4. Datapath Design Computer Organization I 4 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens R-Type Execution 10000000000100000001110001000000 functshamtrdrtrsop ALU computes sum of operands (ALU operation control set by Control). ALU output tranferred to MUX, set to pass through input 0 by Control.

5. Datapath Design Computer Organization I 5 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens R-Type Execution 10000000000100000001110001000000 functshamtrdrtrsop Reg# for $s0 is input to register file write register port. ALU output transferred to register file Write data port. RegWrite control line set by Control.

6. Datapath Design Computer Organization I 6 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens R-Type/Load/Store Datapath How would this execute: lw $s0, 16($s1); 0000 0000 0010 00001000110000100011 16-bit numberrtrsop QTP Alert!!

7. Datapath Design Computer Organization I 7 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Full Datapath How would this execute: beq $s0, $s1, Label0; QTP Alert!!

8. Datapath Design Computer Organization I 8 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Simplified ALU Design Here's a simplified ALU for 4-bit operands that illustrates the control interface we need: InvAInvBFnSelALU Fn 0000AND 0001OR 0010add 0110sub 0111slt 1100NOR Effectively, this ALU has a 4-bit control mechanism for selecting the desired function.

9. Datapath Design Computer Organization I 9 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens ALU Control ALU used for -Load/StoreFunction = add -BranchFunction = subtract -R-typeFunction depends on funct field InvAInvBFnSelALU Fn 0000AND 0001OR 0010add 0110sub 0111slt 1100NOR

10. Datapath Design Computer Organization I 10 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens ALU Control Assume 2-bit control signal ALUOp derived from opcode -Combinational logic derives ALU control opcodeALUOpOperationfunctALU functionALU control lw00load wordXXXXXXadd0010 sw00store wordXXXXXXadd0010 beq01branch equalXXXXXXsubtract0110 R-type10add100000add0010 subtract100010subtract0110 AND100100AND0000 OR100101OR0001 set-on-less-than101010set-on-less-than0111 ALU Control

11. Datapath Design Computer Organization I 11 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens The Main Control Unit Control signals derived from instruction 0rsrtrdshamtfunct 31:265:025:2120:1615:1110:6 35 or 43rsrtaddress 31:2625:2120:1615:0 4rsrtaddress 31:2625:2120:1615:0 R-type Load/ Store Branch opcodealways read read, except for load write for R-type and load sign-extend and add

12. Datapath Design Computer Organization I 12 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Datapath With Control

13. Datapath Design Computer Organization I 13 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Datapath Control Signals RegDstselects instruction bits for write register # Branch1 iff instruction is beq MemRead1 iff memory location is to be read MemtoRegselects source for write data port ALUOpspecifies instruction class to ALU control MemWrite1 iff memory location is to be written ALUSrcselects source for 2 nd operand to ALU RegWrite1 iff register is to be written

14. Datapath Design Computer Organization I 14 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Main Control Truth Table Signal NameR-formatlwswbeq INPUTINPUT Op50110 Op40000 Op30010 Op20001 Op10110 Op00110 OUTPUTOUTPUT RegDst10XX ALUSrc0110 MemtoReg01XX RegWrite1100 MemRead0100 MemWrite0010 Branch0001 ALUOp11000 ALUOp00001 Why are these don't-cares? Why these values?

15. Datapath Design Computer Organization I 15 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Relevancies for R-Type Instruction

16. Datapath Design Computer Organization I 16 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Relevancies for Load Instruction

17. Datapath Design Computer Organization I 17 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Relevancies for beq Instruction

18. Datapath Design Computer Organization I 18 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Implementing Jumps Jump uses word address Update PC with concatenation of -Top 4 bits of old PC -26-bit jump address -00 Need an extra control signal decoded from opcode 2address 31:2625:0 Jump

19. Datapath Design Computer Organization I 19 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Datapath With Jumps Added

20. Datapath Design Computer Organization I 20 CS@VT August 2009 ©2006-09 McQuain, Feng & Ribbens Performance Issues Longest delay determines clock period -Critical path: load instruction -Instruction memory  register file  ALU  data memory  register file Not feasible to vary the clock period for different instructions Violates design principle -Making the common case fast We will improve performance (in 2506) by pipelining