1. Computer Organization & Programming Chapter 6 Single Datapath CPU Architecture

2. How to Design a Processor: step-by-step 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

3. Overview of MIPS All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits optarget address 02631 6 bits26 bits

4. MIPS Instructions

9. Assembly Language Example

10. To summarize:

11. MIPS CPU Implementation Register File Built using D flip-flops

12. Register File

13. Functional units

14. Building the Datapath

15. Control

16. Single/Multi Cycle CPU

17. Control – FSM

18. Executing ADD instruction

19. Executing Load

20. Executing Store

21. Executing BEQ