1. Fall 2006 1 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Computer Organization Lecture 14 Memory hierarchy, locality Memory design

2. Fall 2006 2 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Correction: machine instruction InstructionTypeOp rsrtrdimmed /adr functMachine (hex) add $0, $0, $1 R0x1010na0x00x1400 andi $0, $1, 10f I0xc01na0x10fna0xa90f sll $0, $1 I0x201na 0x2400 lw $0, 323 ($1) I0x410na0x323na0x4b23 beq $0, $1, 17a I0x601na0x17ana0x657a j a64 J0x7na 0xa64na0x7a64 Correction

3. Fall 2006 3 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Any questions on Project 4? Two, 16-bit registers ($0, $1) Two read ports One write port Equal output Due: Nov. 3

4. Fall 2006 4 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Major computer components Five classic computer components

5. Fall 2006 5 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Computer components Input: receives information from external world Output: transmits information to external world Memory: holds programs and data Data path: physical route that carries info Control: coordinates overall flow of info

6. Fall 2006 6 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Memory design goals Unlimited memory size –No upper bound on memory addresses –Not practical or possible: cost, implementation Infinite memory bandwidth –Zero latency memory accesses –Not practical or possible: cost, laws of physics Memory hierarchy can approximate goals

7. Fall 2006 7 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Memory hierarchy Memory closest to CPU is most expensive (fast) but smallest On-chip On-board In-system

8. Fall 2006 8 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Main and cache memory Each memory may contain a subset of the others Cache Main

9. Fall 2006 9 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Storage hierarchy Information flows between layers Less costly Faster Directly accessed Indirectly accessed

10. Fall 2006 10 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Principle of locality Programs access a relatively small portion of their address space at any instant of time Temporal locality: once memory is accessed, its likely to be accessed again (locality in time) Spatial locality: once a memory address is selected, its neighbors are likely to be selected (locality in space)

11. Fall 2006 11 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Memory devices RAM: random access memory –Random access memory (versus sequential) –Read and write –Usually loose contents with power (volatile) ROM: read-only memory –Read only memory –Also random access –Usually non-volatile, or OS protects it

12. Fall 2006 12 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Inputs –Address –Data in (RAM only) –Read/write control (RAM only) –Enable Outputs –Data out –Usually tri-state drivers (on & off, pull-ups) Memory components A D Q E R/W

13. Fall 2006 13 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Tri-state drivers You may connect tri- state outputs together Must assure only one driver enabled at-a- time Common in memory designs, results in MUX function

14. Fall 2006 14 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering General memory design A D Q E R/W A D Q E In 0 E 1 n Address Data R/W Qout (lower bits) (upper bits) decoder memory

15. Fall 2006 15 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Memory design guide Bus lower addresses to all devices Use upper addresses and decoder for device enables (only one active component) Data bus and other control signals sent to all devices No read-write signal for ROM Bus outputs together because they are tri- stated

16. Fall 2006 16 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering ROM design: 64 x 8 Use 32x8 First ROM Second ROM

17. Fall 2006 17 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering ROM 64x8 trace First ROM selected Second ROM selected Float ROM file data is the address

18. Fall 2006 18 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering ROM design: 64 x 16 ? Use 32x8

19. Fall 2006 19 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering ROM 64x16 trace First ROMs selected Second ROMs selected Float

20. Fall 2006 20 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Memory capacity and components c 00 c 0n c 01 c 10 c 1n c 11 c 20 c 2n c 21 c 30 c 3n c 31 c m0 c mn c m1 Greater length (bytes) Greater width (bits) m rows, n columns

21. Fall 2006 21 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering Find the array of components? MemoryComponentLengthWidth 4K x 82K x 4 16M x 321M x 8 4G x 64500M x16

22. Fall 2006 22 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering General memory design A D Q E R/W A D Q E In 0 E 1 n Address Data R/W Qout (lower bits) (upper bits) decoder memory

23. Fall 2006 23 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering RAM design: 16x8 Use 16x4

24. Fall 2006 24 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering RAM 16x8 trace Writing Reading

25. Fall 2006 25 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering RAM design: 32x8 ? Use 16x4

26. Fall 2006 26 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering RAM 32x8 trace Writing Reading

27. Fall 2006 27 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering

28. Fall 2006 28 EE 333 Lillevik 333f06-l14 University of Portland School of Engineering ROM design: 64 x 16 ? Use 32x8