1. ULTRASPARC 2005 INTRODUCTION AND ISA BY JAMES MURITHI

2. OVERVIEW HYPERVISOR DESIGN SCALABILITY IS KEY COMPATIBILITY

3. PROCESSOR ARCHITECTURE INTEGER UNIT FLOATING POINT UNIT

4. IMPLICATIONS NEED FOR MORE INSTRUCTIONS THESE NEED SPECIAL REGISTERS

5. WHATS NEW VIS HYPERPRIVILEDGED MODE CMT

6. ISA RISC PROCESSOR 64 BIT ARCHITECTURE 32 BIT INSTRUCTIONS LOAD STORE ARCHITECTURE INTS, FLOATS, SIMDS BYTE(8BITS), HALF,DOUBLE,QUAD

7. ADDRESSING MODES REGISTER DIRECT AND INDIRECT IMMEDIATE

8. INSTRUCTION FORMATS ENCODED IN 32 BITS IMPLEMENTS SEVERAL MINOR FORMATS TWO ADDRESS THREE ADDRESS NO ADDRESS - CALLS

9. ENCODING 00rdOprs1Set bit Immediate asi?rs2 Class code Branch/Call/Arithmetic/Logical 10rdOprs1Set bitImmediate? asi? rs2 When 0 value is in rs2 when 1 use immediate

10. DATA TYPES FLOATS, INTS SIMD – DEFINES THREE TYPES

11. INSTRUCTIONS REGISTER WINDOW MGT PRIVILEDGED REGISTER ACCESS MEMORY SYNC IMPLEMENTATION DEPENDENT

12. REGISTERS GPR REGISTER WINDOW

13. ? THANK YOU