1. 1 - 1 Digital Signal Controller TMS320F2812 Module 1 : Architecture

2. 1 - 2 C281x Block Diagram 32x32 bit Multiplier Multiplier SectoredFlashSectoredFlash A(18-0) D(15-0) Program Bus Data Bus RAMRAMBootROMBootROM 22 32-bitAuxiliaryRegisters32-bitAuxiliaryRegisters 3 32 bit Timers3 Timers RealtimeJTAGRealtimeJTAG CPU Register Bus R-M-WAtomicALUR-M-WAtomicALU PIE Interrupt Manager 32 32 32 Event Manager A Event Event Manager B Event 12-bit ADC WatchdogWatchdog McBSPMcBSP CAN2.0BCAN2.0B SCI-ASCI-A SCI-BSCI-B SPISPI GPIOGPIO

3. 1 - 3 C28x CPU  32-bit fixed-point DSP  32 x 32 bit fixed-point MAC  Dual 16 x 16 single-cycle fixed- point MAC (DMAC)  32-/64-bit saturation  64/32 and 32/32 modulus division  Fast interrupt service time  Single cycle read-modify-write instructions  Unique real-time debugging capabilities  Upward code compatibility Data Bus 32-bitAuxiliaryRegisters32-bitAuxiliaryRegisters 3 32 bit Timers3 Timers RealtimeJTAGRealtimeJTAG CPU Register Bus R-M-WAtomicALUR-M-WAtomicALU Program Bus  MCU/DSP balancing code density & execution time.  Supports 32-bit instructions for improved execution time;  Supports 16-bit instructions for improved code efficiency PIE Interrupt Manager 32x32 bit Multiplier Multiplier

4. 1 - 4 XT (32) or T/TL MULTIPLIER 32 x 32 or Dual 16 x 16 P (32) or PH/PL AH (16) C28x Multiplier and ALU / Shifters Data Bus Program Bus ALU (32) 32 32 32 32 32 AL (16) 32 32 16/32 8/16 Shift R/L (0-16) ACC (32) AH.MSB AH.LSB AL.MSB AL.LSB 32 Shift R/L (0-16) 32 32 16 8/16/32

5. 1 - 5 C28x Pointer, DP and Memory XAR0XAR1XAR2XAR3XAR4XAR5XAR6XAR7 ARAUMUX Data Memory MUX DP (16) Data Bus Program Bus 6 LSB from IR XARn  32-bits ARn  16-bits 22 32

6. 1 - 6 C28x Internal Bus Structure Data-write Address Bus (32) Program Address Bus (22) Execution R-M-WAtomicALU Real-TimeEmulation&TestEngine Program-read Data Bus (32) JTAG Program Decoder PC XAR0toXAR7 SP DP@X ARAU MPY32x32 XT P ACC ALU Registers Debug Register Bus / Result Bus Data/Program-write Data Bus (32) Data-read Address Bus (32) Data-read Data Bus (32) Memory Data (4G * 16) Program (4M* 16) StandardPeripheralsExternalInterfaces

7. 1 - 7 C28x Atomic Read/Modify/Write Registers ALU / MPY LOAD STORE WRITE READ CPU Mem  Atomic Instructions Benefits:  Simpler programming  Smaller, faster code  Uninterruptible (Atomic)  More efficient compiler AND *XAR2,#1234h 2 words / 1 cycles Atomic Read/Modify/Write MOVAL,*XAR2 ANDAL,#1234h MOV*XAR2,AL DINT EINT 6 words / 6 cycles Standard Load/Store

8. 1 - 8 F 1 F 2 D 1 D 2 R 1 R 2 X C28x Pipeline Protected Pipeline  Order of results are as written in source code  Programmer need not worry about the pipeline 8-stage pipeline F 1 F 2 D 1 D 2 R 1 R 2 X ABC DEFG W W W W W W W W E & G Access same address R 1 R 2 X W D 2 R 1 R 2 X W F1: Instruction Address F2: Instruction Content D1: Decode Instruction D2: Resolve Operand Addr R1: Operand Address R2: Get Operand X: CPU doing “real” work W: store content to memory H

9. 1 - 9 TMS320F2812 Memory Map MO SARAM (1K) M1 SARAM (1K) LO SARAM (4K) L1 SARAM (4K) HO SARAM (8K) Boot ROM (4K) MP/MC=0 BROM vector (32) MP/MC=0 ENPIE=0 OTP (1K) FLASH (128K) reserved PF 0 (2K) reserved PF 1 (4K) reserved PF 2 (4K) reserved PIE vector (256)ENPIE=1 XINT Zone 0 (8K) XINT Zone 1 (8K) XINT Zone 2 (0.5M) XINT Zone 6 (0.5M) XINT Zone 7 (16K) MP/MC=1 XINT Vector-RAM (32) MP/MC=1 ENPIE=0 reserved Data | Program 0x00 0000 0x00 0400 0x00 0800 0x00 0D00 0x00 1000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 0x3D 7800 0x3D 8000 0x3F 8000 0x3F A000 0x3F F000 0x3F FFC0 0x3F C000 0x18 0000 0x10 0000 0x08 0000 0x00 4000 0x00 2000 Data | Program 128-Bit Password CSM: LO, L1 OTP, FLASH reserved 0x3D 7C00

10. 1 - 10 Code Security Module  Prevents reverse engineering and protects valuable intellectual property  128-bit user defined password is stored in Flash  128-bits = 2 128 = 3.4 x 10 38 possible passwords  To try 1 password every 2 cycles at 150 MHz, it would take at least 1.4 x 10 23 years to try all possible combinations! LO SARAM (4K) L1 SARAM (4K) OTP (1K) FLASH (128K) reserved 0x00 8000 0x00 9000 0x00 A000 0x3D 7800 0x3D 8000 128-Bit Password reserved 0x3D 7C00

11. 1 - 11 C28x Fast Interrupt Response Manager  96 dedicated PIE vectors  No software decision making required  Direct access to RAM vectors  Auto flags update  Concurrent auto context save 28x CPU Interrupt logic 28xCPU INTM IFRIER 96 Peripheral Interrupts 12x8 = 96 12 interrupts INT1 to INT12 PIERegisterMap PIE module For 96 interrupts TST0 AHAL PHPL AR1 (L)AR0 (L) DPST1 DBSTATIER PC(msw)PC(lsw) Auto Context Save

12. 1 - 12 C28x / C24x Modes C24x Mode 1 1 C28x Mode 1 0 Test Mode (default) 0 0 Reserved 0 1 OBJMODE AMODE Mode Bits Compiler Option Mode Type  C24x source-compatible mode:  Allows you to run C24x source code which has been reassembled using the C28x code generation tools (need new vectors)  C28x mode:  Can take advantage of all the C28x native features -v28 -v28 -m20 -v27

13. 1 - 13 Reset – Bootloader Reset OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 Boot determined by state of GPIO pins Reset vector fetched from boot ROM 0x3F FFC0 XMPNMC=0 (microcomputer mode) Execution Execution Entry Point H0 SARAM Note: Details of the various boot options will be discussed in the Reset and Interrupts module Bootloader sets OBJMODE = 1 AMODE = 0

14. 1 - 14 Summary  High performance 32-bit DSP  32 x 32 bit or dual 16 x 16 bit MAC  Atomic read-modify-write instructions  8-stage fully protected pipeline  Fast interrupt response manager  128Kw on-chip flash memory  Code security module (CSM)  Two event managers  12-bit ADC module  56 shared GPIO pins  Watchdog timer  Communications peripherals